From 45581e60f03b0255c3a663c2ea96e1e9d1bbbc20 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 5 Oct 2017 00:26:44 -0700 Subject: [PATCH 1/2] Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" This reverts commit 5232a29d7d838ef95d33bfcd2a6fbfde8a82af35, reversing changes made to a2dc13669a3001f5024426eda36ed4c4df8b7ceb. --- src/main/scala/coreplex/RocketCoreplex.scala | 7 +++---- src/main/scala/rocket/HellaCache.scala | 2 -- src/main/scala/system/ExampleRocketSystem.scala | 2 -- src/main/scala/system/TestHarness.scala | 1 - src/main/scala/util/Misc.scala | 16 ---------------- 5 files changed, 3 insertions(+), 25 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 211ccaa5..c106052b 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -3,7 +3,6 @@ package freechips.rocketchip.coreplex import Chisel._ -import chisel3.experimental.dontTouch import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} @@ -115,9 +114,9 @@ trait HasRocketTilesModuleImp extends LazyModuleImp require(vectors.tail.forall(_.getWidth == vectors.head.getWidth)) vectors.head.getWidth } - val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial { + val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial { case SharedMemoryTLEdge => outer.sharedMemoryTLEdge - })))) // dontTouch keeps constant prop from sucking these signals into the tile + }))) // Unconditionally wire up the non-diplomatic tile inputs outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) => @@ -131,7 +130,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) => wire.clock := clock wire.reset := reset - wire.hartid := i.U + wire.hartid := UInt(i) wire.reset_vector := global_reset_vector } } diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index ae316ee4..558e0259 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -4,7 +4,6 @@ package freechips.rocketchip.rocket import Chisel._ -import chisel3.experimental.dontTouch import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.coreplex._ import freechips.rocketchip.diplomacy._ @@ -185,7 +184,6 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle(outer)) - dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable) fifoManagers.foreach { m => diff --git a/src/main/scala/system/ExampleRocketSystem.scala b/src/main/scala/system/ExampleRocketSystem.scala index 981f7a0d..f15c297b 100644 --- a/src/main/scala/system/ExampleRocketSystem.scala +++ b/src/main/scala/system/ExampleRocketSystem.scala @@ -6,7 +6,6 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.coreplex._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util.DontTouch /** Example Top with periphery devices and ports, and a Rocket coreplex */ class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex @@ -26,4 +25,3 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro with HasMasterAXI4MMIOPortModuleImp with HasSlaveAXI4PortModuleImp with HasPeripheryBootROMModuleImp - with DontTouch diff --git a/src/main/scala/system/TestHarness.scala b/src/main/scala/system/TestHarness.scala index 79903b32..e8accb7f 100644 --- a/src/main/scala/system/TestHarness.scala +++ b/src/main/scala/system/TestHarness.scala @@ -14,7 +14,6 @@ class TestHarness()(implicit p: Parameters) extends Module { val dut = Module(LazyModule(new ExampleRocketSystem).module) dut.reset := reset | dut.debug.ndreset - dut.dontTouchPorts() dut.tieOffInterrupts() dut.connectSimAXIMem() dut.connectSimAXIMMIO() diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala index 8ff24fb9..86590d1b 100644 --- a/src/main/scala/util/Misc.scala +++ b/src/main/scala/util/Misc.scala @@ -4,7 +4,6 @@ package freechips.rocketchip.util import Chisel._ -import chisel3.experimental.{dontTouch, RawModule} import freechips.rocketchip.config.Parameters import scala.math._ @@ -22,21 +21,6 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle { } } -// TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts -trait DontTouch { - self: RawModule => - - /** Marks every port as don't touch - * - * @note This method can only be called after the Module has been fully constructed - * (after Module(...)) - */ - def dontTouchPorts(): this.type = { - self.getModulePorts.foreach(dontTouch(_)) - self - } -} - trait Clocked extends Bundle { val clock = Clock() val reset = Bool() From 8da7aabd51a1b5199b49ec1127f454ed1869b2b8 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 5 Oct 2017 00:31:53 -0700 Subject: [PATCH 2/2] tile: supply hartid from RocketTileParams make WithNCores partial configs override rather than append more tiles --- src/main/scala/coreplex/Configs.scala | 6 +++--- src/main/scala/coreplex/RocketCoreplex.scala | 13 +++++++------ src/main/scala/system/Configs.scala | 3 --- src/main/scala/tile/RocketTile.scala | 14 ++++++++------ 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index c320390c..0d932c04 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -45,7 +45,7 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => { icache = Some(ICacheParams( rowBits = site(SystemBusKey).beatBits, blockBytes = site(CacheBlockBytes)))) - List.fill(n)(big) ++ up(RocketTilesKey, site) + List.tabulate(n)(i => big.copy(hartid = i)) } }) @@ -67,7 +67,7 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => { nWays = 1, nTLBEntries = 4, blockBytes = site(CacheBlockBytes)))) - List.fill(n)(small) ++ up(RocketTilesKey, site) + List.tabulate(n)(i => small.copy(hartid = i)) } }) @@ -94,7 +94,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => { nWays = 1, nTLBEntries = 4, blockBytes = site(CacheBlockBytes)))) - List.fill(n)(tiny) ++ up(RocketTilesKey, site) + List.tabulate(n)(i => tiny.copy(hartid = i)) } }) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index c106052b..e7009316 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -24,6 +24,7 @@ trait HasRocketTiles extends HasSystemBus private val crossing = p(RocketCrossing) private val tileParams = p(RocketTilesKey) val nRocketTiles = tileParams.size + val hartIdList = tileParams.map(_.hartid) // Handle interrupts to be routed directly into each tile // TODO: figure out how to merge the localIntNodes and coreIntXbar below @@ -34,8 +35,8 @@ trait HasRocketTiles extends HasSystemBus // Make a wrapper for each tile that will wire it to coreplex devices and crossbars, // according to the specified type of clock crossing. - val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex - val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, tp), i) => + val wiringTuple = localIntNodes.zip(tileParams) + val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case (lip, tp) => val pWithExtra = p.alterPartial { case TileKey => tp case BuildRoCC => tp.rocc @@ -44,19 +45,19 @@ trait HasRocketTiles extends HasSystemBus val wrapper = crossing match { case SynchronousCrossing(params) => { - val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra)) + val wrapper = LazyModule(new SyncRocketTile(tp)(pWithExtra)) sbus.fromSyncTiles(params, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toSyncSlaves(tp.name, tp.externalSlaveBuffers) } wrapper } case AsynchronousCrossing(depth, sync) => { - val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra)) + val wrapper = LazyModule(new AsyncRocketTile(tp)(pWithExtra)) sbus.fromAsyncTiles(depth, sync, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name, tp.externalSlaveBuffers) } wrapper } case RationalCrossing(direction) => { - val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra)) + val wrapper = LazyModule(new RationalRocketTile(tp)(pWithExtra)) sbus.fromRationalTiles(direction, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name, tp.externalSlaveBuffers) } wrapper @@ -127,7 +128,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp } // Default values for tile inputs; may be overriden in other traits - rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) => + rocket_tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => wire.clock := clock wire.reset := reset wire.hartid := UInt(i) diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala index 187e127f..1d5fe758 100644 --- a/src/main/scala/system/Configs.scala +++ b/src/main/scala/system/Configs.scala @@ -63,9 +63,6 @@ class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseCo class DualCoreConfig extends Config( new WithNBigCores(2) ++ new BaseConfig) -class HeterogeneousDualCoreConfig extends Config( - new WithNSmallCores(1) ++ new WithNBigCores(1) ++ new BaseConfig) - class TinyConfig extends Config( new WithNMemoryChannels(0) ++ new WithStatelessBridge ++ diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index b9aaa542..9d9b7b94 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -22,13 +22,14 @@ case class RocketTileParams( trace: Boolean = false, hcfOnUncorrectable: Boolean = false, name: Option[String] = Some("tile"), + hartid: Int = 0, externalMasterBuffers: Int = 0, externalSlaveBuffers: Int = 0) extends TileParams { require(icache.isDefined) require(dcache.isDefined) } -class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(rocketParams)(p) +class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p) with HasExternalInterrupts with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend @@ -39,6 +40,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p private def ofStr(x: String) = Seq(ResourceString(x)) private def ofRef(x: Device) = Seq(ResourceReference(x.label)) + val hartid = rocketParams.hartid val cpuDevice = new Device { def describe(resources: ResourceBindings): Description = { val block = p(CacheBlockBytes) @@ -179,8 +181,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne ptw.io.requestor <> ptwPorts } -abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule { - val rocket = LazyModule(new RocketTile(rtp, hartid)) +abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends LazyModule { + val rocket = LazyModule(new RocketTile(rtp)) val asyncIntNode : IntInwardNode val periphIntNode : IntInwardNode val coreIntNode : IntInwardNode @@ -226,7 +228,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: } } -class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { +class SyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) { val masterNode = optionalMasterBuffer(rocket.masterNode) val slaveNode = optionalSlaveBuffer(rocket.slaveNode) @@ -246,7 +248,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) def outputInterruptXingLatency = 0 } -class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { +class AsyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) { val source = LazyModule(new TLAsyncCrossingSource) source.node :=* rocket.masterNode val masterNode = source.node @@ -272,7 +274,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters def outputInterruptXingLatency = 3 } -class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { +class RationalRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) { val source = LazyModule(new TLRationalCrossingSource) source.node :=* optionalMasterBuffer(rocket.masterNode) val masterNode = source.node