From 9002e7e53299598027f41b95dba1666310923699 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 20 Apr 2017 09:18:39 -0700 Subject: [PATCH] debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. --- src/main/scala/uncore/devices/debug/Debug.scala | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/main/scala/uncore/devices/debug/Debug.scala b/src/main/scala/uncore/devices/debug/Debug.scala index c7b9767b..2e225ed2 100644 --- a/src/main/scala/uncore/devices/debug/Debug.scala +++ b/src/main/scala/uncore/devices/debug/Debug.scala @@ -1097,12 +1097,18 @@ class DMIToTL(implicit p: Parameters) extends LazyModule { val (_, gbits) = edge.Get(src, addr, size) val (_, pfbits) = edge.Put(src, addr, size, io.dmi.req.bits.data) - when (io.dmi.req.fire()) { - assert (io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE || io.dmi.req.bits.op === DMIConsts.dmi_OP_READ, - "Invalid DMI Request Type."); - } + // We force DMI NOPs to go to CONTROL register because + // Inner may be in reset / not have a clock, + // so we force address to be the one that goes to Outer. + // Therefore for a NOP we don't really need to pay the penalty to go + // across the CDC. - tl.a.bits := Mux(io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE, pfbits, gbits); + val (_, nbits) = edge.Put(src, toAddress = (DMI_RegAddrs.DMI_DMCONTROL << 2).U, size, data=0.U, mask = 0.U) + + when (io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE) { tl.a.bits := pfbits + }.elsewhen (io.dmi.req.bits.op === DMIConsts.dmi_OP_READ) { tl.a.bits := gbits + }.otherwise { tl.a.bits := nbits + } tl.a.valid := io.dmi.req.valid io.dmi.req.ready := tl.a.ready