riscv/rocket-chip
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Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR

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This commit is contained in:
Andrew Waterman 2017-04-27 19:46:39 -07:00
parent 7c70aa593e
commit 8fd5ecdff8
1 changed files with 3 additions and 0 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -163,6 +163,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val s2_req = Reg(io.cpu.req.bits)
val s2_req_block_addr = (s2_req.addr >> idxLSB) << idxLSB
val s2_uncached = Reg(Bool())
val s2_uncached_resp_addr = Reg(UInt()) // should be DCE'd in synthesis
when (s1_valid_not_nacked || s1_flush_valid) {
s2_req := s1_req
s2_req.addr := s1_paddr
@ -359,6 +360,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
s2_req.typ := req.typ
s2_req.tag := req.tag
s2_req.addr := Cat(s1_paddr >> beatOffBits /* don't-care */, req.addr(beatOffBits-1, 0))
s2_uncached_resp_addr := req.addr
}
} .elsewhen (grantIsVoluntary) {
assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle!
@ -506,6 +508,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
assert(!s2_valid_hit)
io.cpu.resp.valid := true
io.cpu.resp.bits.replay := true
io.cpu.resp.bits.addr := s2_uncached_resp_addr
}
// load data subword mux/sign extension