riscv/rocket-chip
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Report access exception, not page fault, if page-table walk fails

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This commit is contained in:
Andrew Waterman 2017-03-29 09:49:31 -07:00
parent 25232070ec
commit 8f73a58d90
1 changed files with 9 additions and 4 deletions
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13
src/main/scala/rocket/TLB.scala
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@ -61,6 +61,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val level = UInt(width = log2Ceil(pgLevels)) val level = UInt(width = log2Ceil(pgLevels))
val u = Bool() val u = Bool()
val g = Bool() val g = Bool()
val ae = Bool()
val sw = Bool() val sw = Bool()
val sx = Bool() val sx = Bool()
val sr = Bool() val sr = Bool()
@ -140,9 +141,13 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
newEntry.c := cacheable newEntry.c := cacheable
newEntry.u := pte.u newEntry.u := pte.u
newEntry.g := pte.g newEntry.g := pte.g
newEntry.sr := pte.sr() // if an access exception occurs during PTW, pretend the page has full
newEntry.sw := pte.sw() // permissions so that a page fault will not occur, but clear the
newEntry.sx := pte.sx() // phyiscal memory permissions, so that an access exception will occur.
newEntry.ae := io.ptw.resp.bits.ae
newEntry.sr := pte.sr() || io.ptw.resp.bits.ae
newEntry.sw := pte.sw() || io.ptw.resp.bits.ae
newEntry.sx := pte.sx() || io.ptw.resp.bits.ae
newEntry.pr := prot_r && !io.ptw.resp.bits.ae newEntry.pr := prot_r && !io.ptw.resp.bits.ae
newEntry.pw := prot_w && !io.ptw.resp.bits.ae newEntry.pw := prot_w && !io.ptw.resp.bits.ae
newEntry.px := prot_x && !io.ptw.resp.bits.ae newEntry.px := prot_x && !io.ptw.resp.bits.ae
@ -154,7 +159,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val plru = new PseudoLRU(normalEntries) val plru = new PseudoLRU(normalEntries)
val repl_waddr = Mux(!valid(normalEntries-1, 0).andR, PriorityEncoder(~valid(normalEntries-1, 0)), plru.replace) val repl_waddr = Mux(!valid(normalEntries-1, 0).andR, PriorityEncoder(~valid(normalEntries-1, 0)), plru.replace)
val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.sum, UInt(0), entries.map(_.u).asUInt), entries.map(_.u).asUInt) val priv_ok = entries.map(_.ae).asUInt | Mux(priv_s, ~Mux(io.ptw.status.sum, UInt(0), entries.map(_.u).asUInt), entries.map(_.u).asUInt)
val r_array = Cat(true.B, priv_ok & (entries.map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.sx).asUInt, UInt(0)))) val r_array = Cat(true.B, priv_ok & (entries.map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.sx).asUInt, UInt(0))))
val w_array = Cat(true.B, priv_ok & entries.map(_.sw).asUInt) val w_array = Cat(true.B, priv_ok & entries.map(_.sw).asUInt)
val x_array = Cat(true.B, priv_ok & entries.map(_.sx).asUInt) val x_array = Cat(true.B, priv_ok & entries.map(_.sx).asUInt)