riscv/rocket-chip
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BusBlocker: change default policy to deny

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This commit is contained in:
Wesley W. Terpstra 2017-08-08 14:19:59 -07:00
parent 0d76e96b88
commit 8f261adc6b
1 changed files with 2 additions and 3 deletions
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5
src/main/scala/devices/tilelink/BusBlocker.scala
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@ -62,10 +62,9 @@ object DevicePMP
def apply(addressBits: Int) = { def apply(addressBits: Int) = {
val out = Wire(new DevicePMP(DevicePMPParams(addressBits))) val out = Wire(new DevicePMP(DevicePMPParams(addressBits)))
out.l := UInt(0) out.l := UInt(0)
out.a := UInt(1) // TOR out.a := UInt(0)
out.r := UInt(0) out.r := UInt(0)
out.w := UInt(0) out.w := UInt(0)
out.addr_hi := ~UInt(0, width=addressBits-12)
out out
} }
} }
@ -101,7 +100,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
val lte = Bool(false) +: pmps.map(in.a.bits.address < _.address) val lte = Bool(false) +: pmps.map(in.a.bits.address < _.address)
val sel = (pmps.map(_.a) zip (lte.init zip lte.tail)) map { case (a, (l, r)) => a(0) && !l && r } val sel = (pmps.map(_.a) zip (lte.init zip lte.tail)) map { case (a, (l, r)) => a(0) && !l && r }
val ok = pmps.map(p => (p.r(0) || !needR) && (p.w(0) || !needW)) val ok = pmps.map(p => (p.r(0) || !needR) && (p.w(0) || !needW))
val allow = PriorityMux(sel :+ Bool(true), ok :+ Bool(true)) // no match => allow val allow = PriorityMux(sel :+ Bool(true), ok :+ Bool(false)) // no match => deny
bar.module.io.bypass := !allow bar.module.io.bypass := !allow
} }