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Remove ClockToSignal and vice-versa

Clock.asUInt and Bool.asClock now suffice.
This commit is contained in:
Andrew Waterman 2016-09-21 16:17:14 -07:00
parent 2ab61f1a71
commit 8e63f4a1a5
4 changed files with 0 additions and 79 deletions

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@ -85,43 +85,3 @@ object AsyncIrrevocableFrom
PostQueueIrrevocablize(AsyncDecoupledFrom(from_clock, from_reset, from_source, depth, sync)) PostQueueIrrevocablize(AsyncDecoupledFrom(from_clock, from_reset, from_source, depth, sync))
} }
} }
/** Because Chisel/FIRRTL does not allow us
* to directly assign clocks from Signals,
* we need this black box module.
* This may even be useful because some back-end
* flows like to have this sort of transition
* flagged with a special cell or module anyway.
*/
class SignalToClock extends BlackBox {
val io = new Bundle {
val signal_in = Bool(INPUT)
val clock_out = Clock(OUTPUT)
}
// io.clock_out := io.signal_in
}
object SignalToClock {
def apply(signal: Bool): Clock = {
val s2c = Module(new SignalToClock)
s2c.io.signal_in := signal
s2c.io.clock_out
}
}
class ClockToSignal extends BlackBox {
val io = new Bundle {
val clock_in = Clock(INPUT)
val signal_out = Bool(OUTPUT)
}
}
object ClockToSignal {
def apply(clk: Clock): Bool = {
val c2s = Module(new ClockToSignal)
c2s.io.clock_in := clk
c2s.io.signal_out
}
}

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@ -10,8 +10,6 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
$(base_dir)/vsrc/AsyncResetReg.v \ $(base_dir)/vsrc/AsyncResetReg.v \
$(base_dir)/vsrc/AsyncSetReg.v \ $(base_dir)/vsrc/AsyncSetReg.v \
$(base_dir)/vsrc/ClockDivider.v \ $(base_dir)/vsrc/ClockDivider.v \
$(base_dir)/vsrc/ClockToSignal.v \
$(base_dir)/vsrc/SignalToClock.v \
sim_vsrcs = \ sim_vsrcs = \

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@ -1,19 +0,0 @@
/* This blackbox is needed by
* Chisel in order to do type conversion.
* It may be useful for some synthesis flows
* as well which require special
* flagging on conversion from data to clock.
*/
module ClockToSignal(
output signal_out,
input clock_in
);
assign signal_out = clock_in;
endmodule // ClockToSignal

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@ -1,18 +0,0 @@
/* This blackbox is needed by
* Chisel in order to do type conversion.
* It may be useful for some synthesis flows
* as well which require special
* flagging on conversion from data to clock.
*/
module SignalToClock (
output clock_out,
input signal_in
);
assign clock_out = signal_in;
endmodule // SignalToClock