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tilelink2: add types for a TL clockless interface

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This commit is contained in:
Wesley W. Terpstra 2016-09-29 15:34:21 -07:00
parent 02ce8c2ca4
commit 8e4c1e567c
3 changed files with 80 additions and 7 deletions
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22
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -190,7 +190,7 @@ object TLBundle
def apply(params: TLBundleParameters) = new TLBundle(params) def apply(params: TLBundleParameters) = new TLBundle(params)
} }
class IrrevocableSnoop[+T <: Data](gen: T) extends Bundle final class IrrevocableSnoop[+T <: Data](gen: T) extends Bundle
{ {
val ready = Bool() val ready = Bool()
val valid = Bool() val valid = Bool()
@ -232,3 +232,23 @@ object TLBundleSnoop
out out
} }
} }
final class AsyncBundle[T <: Data](depth: Int, gen: T) extends Bundle
{
require (isPow2(depth))
val ridx = UInt(width = log2Up(depth)+1).flip
val widx = UInt(width = log2Up(depth)+1)
val mem = Vec(depth, gen)
override def cloneType: this.type = new AsyncBundle(depth, gen).asInstanceOf[this.type]
}
class TLAsyncBundleBase(params: TLAsyncBundleParameters) extends GenericParameterizedBundle(params)
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(params.depth, new TLBundleA(params.base))
val b = new AsyncBundle(params.depth, new TLBundleB(params.base)).flip
val c = new AsyncBundle(params.depth, new TLBundleC(params.base))
val d = new AsyncBundle(params.depth, new TLBundleD(params.base)).flip
val e = new AsyncBundle(params.depth, new TLBundleE(params.base))
}

26
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -401,6 +401,17 @@ case class TLBundleParameters(
max(sizeBits, x.sizeBits)) max(sizeBits, x.sizeBits))
} }
object TLBundleParameters
{
def apply(client: TLClientPortParameters, manager: TLManagerPortParameters) =
new TLBundleParameters(
addrHiBits = log2Up(manager.maxAddress + 1) - log2Ceil(manager.beatBytes),
dataBits = manager.beatBytes * 8,
sourceBits = log2Up(client.endSourceId),
sinkBits = log2Up(manager.endSinkId),
sizeBits = log2Up(log2Ceil(max(client.maxTransfer, manager.maxTransfer))+1))
}
case class TLEdgeParameters( case class TLEdgeParameters(
client: TLClientPortParameters, client: TLClientPortParameters,
manager: TLManagerPortParameters) manager: TLManagerPortParameters)
@ -411,10 +422,13 @@ case class TLEdgeParameters(
// Sanity check the link... // Sanity check the link...
require (maxTransfer >= manager.beatBytes) require (maxTransfer >= manager.beatBytes)
val bundle = TLBundleParameters( val bundle = TLBundleParameters(client, manager)
addrHiBits = log2Up(manager.maxAddress + 1) - log2Ceil(manager.beatBytes), }
dataBits = manager.beatBytes * 8,
sourceBits = log2Up(client.endSourceId), case class TLAsyncManagerPortParameters(depth: Int, base: TLManagerPortParameters) { require (isPow2(depth)) }
sinkBits = log2Up(manager.endSinkId), case class TLAsyncClientPortParameters(base: TLClientPortParameters)
sizeBits = log2Up(maxLgSize+1)) case class TLAsyncBundleParameters(depth: Int, base: TLBundleParameters) { require (isPow2(depth)) }
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters)
{
val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base))
} }

39
src/main/scala/uncore/tilelink2/TLNodes.scala
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@ -71,3 +71,42 @@ class TLInputNodeTest extends UnitTest(500000) {
io.finished := Module(fuzzer.module).io.finished io.finished := Module(fuzzer.module).io.finished
} }
object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
def bundleO(eo: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = {
require (eo.size == 1)
Vec(eo.size, new TLAsyncBundle(eo(0).bundle))
}
def bundleI(ei: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = {
require (ei.size == 1)
Vec(ei.size, new TLAsyncBundle(ei(0).bundle)).flip
}
def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => { bi <> bo })
}
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
case class TLAsyncSourceNode() extends MixedNode(TLImp, TLAsyncImp)(
dFn = { case (1, s) => s.map(TLAsyncClientPortParameters(_)) },
uFn = { case (1, s) => s.map(_.base) },
numPO = 1 to 1,
numPI = 1 to 1)
case class TLAsyncSinkNode(depth: Int) extends MixedNode(TLAsyncImp, TLImp)(
dFn = { case (1, s) => s.map(_.base) },
uFn = { case (1, s) => s.map(TLAsyncManagerPortParameters(depth, _)) },
numPO = 1 to 1,
numPI = 1 to 1)