riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: add types for a TL clockless interface

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-29 15:34:21 -07:00
parent 02ce8c2ca4
commit 8e4c1e567c
3 changed files with 80 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/main/scala/uncore/tilelink2/Bundles.scala
View File

@ -190,7 +190,7 @@ object TLBundle
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class IrrevocableSnoop[+T <: Data](gen: T) extends Bundle
final class IrrevocableSnoop[+T <: Data](gen: T) extends Bundle
{
val ready = Bool()
val valid = Bool()
@ -232,3 +232,23 @@ object TLBundleSnoop
out
}
}
final class AsyncBundle[T <: Data](depth: Int, gen: T) extends Bundle
{
require (isPow2(depth))
val ridx = UInt(width = log2Up(depth)+1).flip
val widx = UInt(width = log2Up(depth)+1)
val mem = Vec(depth, gen)
override def cloneType: this.type = new AsyncBundle(depth, gen).asInstanceOf[this.type]
}
class TLAsyncBundleBase(params: TLAsyncBundleParameters) extends GenericParameterizedBundle(params)
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(params.depth, new TLBundleA(params.base))
val b = new AsyncBundle(params.depth, new TLBundleB(params.base)).flip
val c = new AsyncBundle(params.depth, new TLBundleC(params.base))
val d = new AsyncBundle(params.depth, new TLBundleD(params.base)).flip
val e = new AsyncBundle(params.depth, new TLBundleE(params.base))
}