From 8e4be40efc22126fa4a93a48e6817b09d77fa037 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 27 Jun 2017 12:46:49 -0700 Subject: [PATCH] Propagate wb_reg_rs2 for sfence ASID This would have been a bug if we supported ASIDs. --- src/main/scala/rocket/Rocket.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/Rocket.scala b/src/main/scala/rocket/Rocket.scala index a8189831..498c4a2f 100644 --- a/src/main/scala/rocket/Rocket.scala +++ b/src/main/scala/rocket/Rocket.scala @@ -356,6 +356,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || Vec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_ctrl.mem_type) + val ex_sfence = Bool(usingVM) && ex_ctrl.mem && ex_ctrl.mem_cmd === M_SFENCE val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause))) @@ -387,7 +388,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) - mem_reg_sfence := Bool(usingVM) && ex_ctrl.mem && ex_ctrl.mem_cmd === M_SFENCE + mem_reg_sfence := ex_sfence mem_reg_btb_hit := ex_reg_btb_hit when (ex_reg_btb_hit) { mem_reg_btb_resp := ex_reg_btb_resp } mem_reg_flush_pipe := ex_reg_flush_pipe @@ -397,7 +398,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) mem_reg_inst := ex_reg_inst mem_reg_pc := ex_reg_pc mem_reg_wdata := alu.io.out - when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc)) { + when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { val typ = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_ctrl.mem_type) mem_reg_rs2 := new uncore.util.StoreGen(typ, 0.U, ex_rs(1), coreDataBytes).data } @@ -431,7 +432,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) wb_reg_rvc := mem_reg_rvc wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) - when (mem_ctrl.rocc) { + when (mem_ctrl.rocc || mem_reg_sfence) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause