riscv/rocket-chip
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Use 1 MHz as default timebase (#628)

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Defaulting to 0 prevents Linux from booting
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Andrew Waterman 2017-03-28 19:59:56 -07:00 committed by Wesley W. Terpstra
parent 44fb3be7d0
commit 8dfbf4532a
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocketchip/Configs.scala
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@ -24,7 +24,8 @@ class BasePlatformConfig extends Config((site, here, up) => {
// DTS descriptive parameters // DTS descriptive parameters
case DTSModel => "ucbbar,rocketchip-unknown" case DTSModel => "ucbbar,rocketchip-unknown"
case DTSCompat => Nil case DTSCompat => Nil
case DTSTimebase => BigInt(0) case DTSTimebase => BigInt(1000000) // 1 MHz
case RTCPeriod => 1000 // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz
// TileLink connection parameters // TileLink connection parameters
case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args))) case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
case TLFuzzReadyValid => false case TLFuzzReadyValid => false
@ -40,7 +41,6 @@ class BasePlatformConfig extends Config((site, here, up) => {
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4) case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4) case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2) case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
}) })
/** Actual elaboratable target Configs */ /** Actual elaboratable target Configs */