riscv/rocket-chip
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new D$ with better QoR and AMO pipelining

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Vector unit is disabled because nack handling needs to be fixed.
This commit is contained in:
Andrew Waterman 2012-11-16 02:39:33 -08:00
parent a90a1790a5
commit 8dce89703a
11 changed files with 738 additions and 956 deletions
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11
rocket/src/main/scala/arbiter.scala
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@ -43,8 +43,7 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp
io.requestor(i).xcpt := io.mem.xcpt io.requestor(i).xcpt := io.mem.xcpt
resp.bits := io.mem.resp.bits resp.bits := io.mem.resp.bits
resp.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n)) resp.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
resp.bits.miss := io.mem.resp.bits.miss && tag_hit resp.bits.nack := io.mem.resp.bits.nack && tag_hit
resp.bits.nack := io.mem.resp.bits.nack && r_valid(i)
resp.bits.replay := io.mem.resp.bits.replay && tag_hit resp.bits.replay := io.mem.resp.bits.replay && tag_hit
} }
} }
@ -90,10 +89,15 @@ class MemArbiter(n: Int) extends Component {
for (i <- 1 until n) for (i <- 1 until n)
io.requestor(i).xact_finish.ready := io.requestor(i-1).xact_finish.ready && !io.requestor(i-1).xact_finish.valid io.requestor(i).xact_finish.ready := io.requestor(i-1).xact_finish.ready && !io.requestor(i-1).xact_finish.valid
io.mem.xact_rep.ready := Bool(false)
for (i <- 0 until n) for (i <- 0 until n)
{ {
val tag = io.mem.xact_rep.bits.tile_xact_id val tag = io.mem.xact_rep.bits.tile_xact_id
io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2Up(n)-1,0) === UFix(i) io.requestor(i).xact_rep.valid := Bool(false)
when (tag(log2Up(n)-1,0) === UFix(i)) {
io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid
io.mem.xact_rep.ready := io.requestor(i).xact_rep.ready
}
io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits
io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2Up(n)) io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2Up(n))
} }
@ -107,5 +111,4 @@ class MemArbiter(n: Int) extends Component {
} }
io.mem.xact_abort.ready := Bool(true) io.mem.xact_abort.ready := Bool(true)
io.mem.xact_rep.ready := Bool(true)
} }

34
rocket/src/main/scala/consts.scala
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@ -72,35 +72,6 @@ trait ScalarOpConstants {
val RA = UFix(1, 5); val RA = UFix(1, 5);
} }
trait MemoryOpConstants {
val MT_X = Bits("b???", 3);
val MT_B = Bits("b000", 3);
val MT_H = Bits("b001", 3);
val MT_W = Bits("b010", 3);
val MT_D = Bits("b011", 3);
val MT_BU = Bits("b100", 3);
val MT_HU = Bits("b101", 3);
val MT_WU = Bits("b110", 3);
val M_X = Bits("b????", 4);
val M_XRD = Bits("b0000", 4); // int load
val M_XWR = Bits("b0001", 4); // int store
val M_PFR = Bits("b0010", 4); // prefetch with intent to read
val M_PFW = Bits("b0011", 4); // prefetch with intent to write
val M_FLA = Bits("b0100", 4); // write back and invlaidate all lines
val M_FENCE = Bits("b0101", 4); // memory fence
val M_INV = Bits("b0110", 4); // write back and invalidate line
val M_CLN = Bits("b0111", 4); // write back line
val M_XA_ADD = Bits("b1000", 4);
val M_XA_SWAP = Bits("b1001", 4);
val M_XA_AND = Bits("b1010", 4);
val M_XA_OR = Bits("b1011", 4);
val M_XA_MIN = Bits("b1100", 4);
val M_XA_MAX = Bits("b1101", 4);
val M_XA_MINU = Bits("b1110", 4);
val M_XA_MAXU = Bits("b1111", 4);
}
trait PCRConstants { trait PCRConstants {
val PCR_X = Bits("b???", 3) val PCR_X = Bits("b???", 3)
val PCR_N = Bits(0,3) val PCR_N = Bits(0,3)
@ -109,11 +80,6 @@ trait PCRConstants {
val PCR_C = Bits(6,3) // clearpcr val PCR_C = Bits(6,3) // clearpcr
val PCR_S = Bits(7,3) // setpcr val PCR_S = Bits(7,3) // setpcr
val SYNC_X = Bits("b??", 2)
val SYNC_N = Bits(0,2);
val SYNC_D = Bits(1,2);
val SYNC_I = Bits(2,2);
val PCR_STATUS = UFix( 0, 5); val PCR_STATUS = UFix( 0, 5);
val PCR_EPC = UFix( 1, 5); val PCR_EPC = UFix( 1, 5);
val PCR_BADVADDR = UFix( 2, 5); val PCR_BADVADDR = UFix( 2, 5);

6
rocket/src/main/scala/core.scala
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@ -114,11 +114,11 @@ class Core(implicit conf: RocketConfiguration) extends Component
dmem(2).req.bits.data := Reg(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data) dmem(2).req.bits.data := Reg(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data)
vu.io.dmem_req.ready := dmem(2).req.ready vu.io.dmem_req.ready := dmem(2).req.ready
vu.io.dmem_resp.valid := Reg(dmem(2).resp.valid) vu.io.dmem_resp.valid := dmem(2).resp.valid
vu.io.dmem_resp.bits.nack := dmem(2).resp.bits.nack vu.io.dmem_resp.bits.nack := dmem(2).resp.bits.nack
vu.io.dmem_resp.bits.data := dmem(2).resp.bits.data_subword vu.io.dmem_resp.bits.data := dmem(2).resp.bits.data_subword
vu.io.dmem_resp.bits.tag := Reg(dmem(2).resp.bits.tag) vu.io.dmem_resp.bits.tag := dmem(2).resp.bits.tag
vu.io.dmem_resp.bits.typ := Reg(dmem(2).resp.bits.typ) vu.io.dmem_resp.bits.typ := dmem(2).resp.bits.typ
// share vector integer multiplier with rocket // share vector integer multiplier with rocket
dpath.io.vec_imul_req <> vu.io.cp_imul_req dpath.io.vec_imul_req <> vu.io.cp_imul_req

599
rocket/src/main/scala/ctrl.scala
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@ -26,8 +26,9 @@ class ioCtrlDpath extends Bundle()
val sel_wa = Bool(OUTPUT); val sel_wa = Bool(OUTPUT);
val sel_wb = UFix(OUTPUT, 3); val sel_wb = UFix(OUTPUT, 3);
val pcr = UFix(OUTPUT, 3) val pcr = UFix(OUTPUT, 3)
val wb_eret = Bool(OUTPUT); val eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT); val mem_load = Bool(OUTPUT);
val wb_load = Bool(OUTPUT)
val ex_fp_val= Bool(OUTPUT); val ex_fp_val= Bool(OUTPUT);
val mem_fp_val= Bool(OUTPUT); val mem_fp_val= Bool(OUTPUT);
val ex_wen = Bool(OUTPUT); val ex_wen = Bool(OUTPUT);
@ -44,23 +45,20 @@ class ioCtrlDpath extends Bundle()
// inputs from datapath // inputs from datapath
val inst = Bits(INPUT, 32); val inst = Bits(INPUT, 32);
val jalr_eq = Bool(INPUT) val jalr_eq = Bool(INPUT)
val br_eq = Bool(INPUT); val ex_br_type = Bits(OUTPUT, 3)
val br_lt = Bool(INPUT); val ex_br_taken = Bool(INPUT)
val br_ltu = Bool(INPUT);
val div_rdy = Bool(INPUT); val div_rdy = Bool(INPUT);
val div_result_val = Bool(INPUT); val div_result_val = Bool(INPUT);
val mul_rdy = Bool(INPUT); val mul_rdy = Bool(INPUT);
val mul_result_val = Bool(INPUT); val mul_result_val = Bool(INPUT);
val mem_wb = Bool(INPUT); val mem_ll_wb = Bool(INPUT)
val mem_ll_waddr = UFix(INPUT, 5)
val ex_waddr = UFix(INPUT, 5); // write addr from execute stage val ex_waddr = UFix(INPUT, 5); // write addr from execute stage
val mem_waddr = UFix(INPUT, 5); // write addr from memory stage val mem_waddr = UFix(INPUT, 5); // write addr from memory stage
val wb_waddr = UFix(INPUT, 5); // write addr from writeback stage val wb_waddr = UFix(INPUT, 5); // write addr from writeback stage
val status = Bits(INPUT, 32); val status = Bits(INPUT, 32);
val sboard_clr = Bool(INPUT);
val sboard_clra = UFix(INPUT, 5);
val fp_sboard_clr = Bool(INPUT); val fp_sboard_clr = Bool(INPUT);
val fp_sboard_clra = UFix(INPUT, 5); val fp_sboard_clra = UFix(INPUT, 5);
val fp_sboard_wb_waddr = UFix(INPUT, 5);
val irq_timer = Bool(INPUT); val irq_timer = Bool(INPUT);
val irq_ipi = Bool(INPUT); val irq_ipi = Bool(INPUT);
val pcr_replay = Bool(INPUT) val pcr_replay = Bool(INPUT)
@ -71,12 +69,13 @@ abstract trait DecodeConstants
val xpr64 = Y; val xpr64 = Y;
val decode_default = val decode_default =
// jalr eret // fence.i
// fp_val | renx2 div_val | syscall // jalr | eret
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // fp_val | renx2 div_val | | syscall
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next // | vec_val | | renx1 mem_val mul_val | wen pcr | | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,MUL_X, X,X,WA_X, WB_X, PCR_X,SYNC_X,X,X,X,X) List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,MUL_X, X,X,WA_X, WB_X, PCR_X,N,X,X,X,X)
val table: Array[(Bits, List[Bits])] val table: Array[(Bits, List[Bits])]
} }
@ -84,237 +83,239 @@ abstract trait DecodeConstants
object XDecode extends DecodeConstants object XDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// jalr eret // fence.i
// fp_val | renx2 div_val | syscall // jalr | eret
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // fp_val | renx2 div_val | | syscall
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next // | vec_val | | renx1 mem_val mul_val | wen pcr | | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
J-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), J-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
JAL-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RA,WB_PC, PCR_N,SYNC_N,N,N,N,N), JAL-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RA,WB_PC, PCR_N,N,N,N,N,N),
JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N), JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N),
JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N), JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N),
JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N), JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N),
RDNPC-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N), RDNPC-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N),
LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LW-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LW-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LBU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LBU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LHU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LHU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SB-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), SB-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N),
SH-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), SH-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N),
SW-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), SW-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N),
SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N),
AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
LUI-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), LUI-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLTU,N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLTU,N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
ORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), ORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
XORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), XORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SUB, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SUB, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLTU,N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLTU,N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
riscvAND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), riscvAND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
riscvOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), riscvOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
riscvXOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), riscvXOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SUB, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SUB, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SL, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_H, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_H, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HU, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HU, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HSU,N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HSU,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,Y,N,N), SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,Y,N,N),
SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_S,SYNC_N,N,N,Y,Y), SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_S,N,N,N,Y,Y),
CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_C,SYNC_N,N,N,Y,Y), CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_C,N,N,N,Y,Y),
ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,Y,N,Y,N), ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,Y,N,Y,N),
FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_D,N,N,N,N), FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FLA, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_I,N,N,N,Y), FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,Y,N,N,N,Y),
CFLUSH-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FLA, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,Y), MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_F,N,N,N,Y,Y),
MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_F,SYNC_N,N,N,Y,Y), MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_T,N,N,N,Y,Y),
MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_T,SYNC_N,N,N,Y,Y), RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,N,N,N,N,N),
RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N), RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,N,N,N,N,N),
RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N), RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_IRT,PCR_N,N,N,N,N,N))
RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_IRT,PCR_N,SYNC_N,N,N,N,N))
} }
object FDecode extends DecodeConstants object FDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// jalr eret // fence.i
// fp_val | renx2 div_val | syscall // jalr | eret
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // fp_val | renx2 div_val | | syscall
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next // | vec_val | | renx1 mem_val mul_val | wen pcr | | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
FCVT_S_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_S_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_D_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_D_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSGNJ_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSGNJ_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSGNJ_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSGNJ_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSGNJX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSGNJX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSGNJX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSGNJX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSGNJN_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSGNJN_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSGNJN_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSGNJN_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMIN_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMIN_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMIN_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMIN_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMAX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMAX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMAX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMAX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMUL_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMUL_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMUL_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMUL_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FMSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FMSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FNMADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FNMADD_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FNMADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FNMADD_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FNMSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FNMSUB_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FNMSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FNMSUB_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MFTX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MFTX_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MFTX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MFTX_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_W_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_W_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_W_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_W_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_WU_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_WU_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_WU_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_WU_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_L_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_L_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_L_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_L_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_LU_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_LU_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_LU_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_LU_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FEQ_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FEQ_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FEQ_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FEQ_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FLT_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FLT_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FLT_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FLT_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FLE_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FLE_S-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FLE_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FLE_D-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MXTF_S-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MXTF_S-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MXTF_D-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MXTF_D-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_S_W-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_S_W-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_D_W-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_D_W-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_S_WU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_S_WU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_D_WU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_D_WU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_S_L-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_S_L-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_D_L-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_D_L-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_S_LU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_S_LU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FCVT_D_LU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), FCVT_D_LU-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MFFSR-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MFFSR-> List(FPU_Y,Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
MTFSR-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MTFSR-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FLW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), FLW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
FLD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), FLD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
FSW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), FSW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N),
FSD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N)) FSD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N))
} }
object VDecode extends DecodeConstants object VDecode extends DecodeConstants
{ {
val table = Array( val table = Array(
// jalr eret // fence.i
// fp_val | renx2 div_val | syscall // jalr | eret
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // fp_val | renx2 div_val | | syscall
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next // | vec_val | | renx1 mem_val mul_val | wen pcr | | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
VVCFGIVL-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y), VVCFGIVL-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,Y),
VVCFG-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y), VVCFG-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,Y),
VSETVL-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y), VSETVL-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,Y),
VF-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), VF-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N),
VMVV-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), VMVV-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
VMSV-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VMSV-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFMVV-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), VFMVV-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N),
FENCE_V_L-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N), FENCE_V_L-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
FENCE_V_G-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_D,N,N,N,N), FENCE_V_G-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,N,N),
VLD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLWU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLWU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLH-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLH-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLHU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLHU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLB-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLB-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLBU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLBU-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSH-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSH-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSB-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSB-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFLD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFLD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFLW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFLW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFSD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFSD-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFSW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFSW-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTWU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTWU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTH-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTH-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTHU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTHU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTB-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTB-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VLSTBU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VLSTBU-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSSTH-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSSTH-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VSSTB-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VSSTB-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFLSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFLSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFLSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFLSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFSSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFSSTD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VFSSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), VFSSTW-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N),
VENQCMD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N), VENQCMD-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N),
VENQIMM1-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N), VENQIMM1-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N),
VENQIMM2-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N), VENQIMM2-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N),
VENQCNT-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N), VENQCNT-> List(VEC_Y,N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N),
VXCPTEVAC-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,Y,N), VXCPTEVAC-> List(VEC_Y,N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N),
VXCPTKILL-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,N), VXCPTKILL-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,Y,N),
VXCPTHOLD-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,N)) VXCPTHOLD-> List(VEC_Y,N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,N,N,N,Y,N))
} }
class Control(implicit conf: RocketConfiguration) extends Component class Control(implicit conf: RocketConfiguration) extends Component
@ -342,7 +343,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
val id_int_val :: id_fp_val :: id_vec_val :: id_br_type :: id_jalr :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs val id_int_val :: id_fp_val :: id_vec_val :: id_br_type :: id_jalr :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0 val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
val id_pcr :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1 val id_pcr :: id_fence_i :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
val id_raddr3 = io.dpath.inst(16,12); val id_raddr3 = io.dpath.inst(16,12);
val id_raddr2 = io.dpath.inst(21,17); val id_raddr2 = io.dpath.inst(21,17);
@ -395,13 +396,13 @@ class Control(implicit conf: RocketConfiguration) extends Component
val wb_reg_wen = Reg(resetVal = Bool(false)) val wb_reg_wen = Reg(resetVal = Bool(false))
val wb_reg_fp_wen = Reg(resetVal = Bool(false)) val wb_reg_fp_wen = Reg(resetVal = Bool(false))
val wb_reg_flush_inst = Reg(resetVal = Bool(false)) val wb_reg_flush_inst = Reg(resetVal = Bool(false))
val wb_reg_mem_val = Reg(resetVal = Bool(false))
val wb_reg_eret = Reg(resetVal = Bool(false)) val wb_reg_eret = Reg(resetVal = Bool(false))
val wb_reg_xcpt = Reg(resetVal = Bool(false)) val wb_reg_xcpt = Reg(resetVal = Bool(false))
val wb_reg_replay = Reg(resetVal = Bool(false)) val wb_reg_replay = Reg(resetVal = Bool(false))
val wb_reg_replay_next = Reg(resetVal = Bool(false)) val wb_reg_replay_next = Reg(resetVal = Bool(false))
val wb_reg_cause = Reg(){UFix()} val wb_reg_cause = Reg(){UFix()}
val wb_reg_fp_val = Reg(resetVal = Bool(false)) val wb_reg_fp_val = Reg(resetVal = Bool(false))
val wb_reg_dcache_miss = Reg(io.dmem.resp.bits.miss || io.dmem.resp.bits.nack, resetVal = Bool(false))
val wb_reg_div_mul_val = Reg(resetVal = Bool(false)) val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
val take_pc = Bool() val take_pc = Bool()
@ -509,7 +510,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
ex_reg_wen := id_wen ex_reg_wen := id_wen
ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen
ex_reg_eret := id_eret.toBool; ex_reg_eret := id_eret.toBool;
ex_reg_flush_inst := (id_sync === SYNC_I); ex_reg_flush_inst := id_fence_i
ex_reg_fp_val := id_fp_val ex_reg_fp_val := id_fp_val
ex_reg_vec_val := id_vec_val.toBool ex_reg_vec_val := id_vec_val.toBool
ex_reg_replay_next := id_replay_next ex_reg_replay_next := id_replay_next
@ -519,20 +520,22 @@ class Control(implicit conf: RocketConfiguration) extends Component
ex_reg_xcpt := id_xcpt ex_reg_xcpt := id_xcpt
} }
val br_taken = // replay inst in ex stage
Mux(ex_reg_br_type === BR_EQ, io.dpath.br_eq, val wb_dcache_miss = wb_reg_mem_val && (wb_reg_wen || wb_reg_fp_wen) && !io.dmem.resp.valid
Mux(ex_reg_br_type === BR_NE, ~io.dpath.br_eq, val replay_ex = wb_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
Mux(ex_reg_br_type === BR_LT, io.dpath.br_lt, ex_reg_mem_val && !io.dmem.req.ready ||
Mux(ex_reg_br_type === BR_GE, ~io.dpath.br_lt, ex_reg_div_val && !io.dpath.div_rdy ||
Mux(ex_reg_br_type === BR_LTU, io.dpath.br_ltu, ex_reg_mul_val && !io.dpath.mul_rdy ||
Mux(ex_reg_br_type === BR_GEU, ~io.dpath.br_ltu, mem_reg_replay_next
ex_reg_br_type === BR_J)))))) ctrl_killx := take_pc_wb || replay_ex
val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === br_taken)
val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === io.dpath.ex_br_taken)
val (ex_xcpt, ex_cause) = checkExceptions(List( val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause), (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
(ex_reg_fp_val && io.fpu.illegal_rm, UFix(2)))) (ex_reg_fp_val && io.fpu.illegal_rm, UFix(2))))
mem_reg_replay := replay_ex && !take_pc_wb;
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb
when (ex_xcpt) { mem_reg_cause := ex_cause } when (ex_xcpt) { mem_reg_cause := ex_cause }
mem_reg_div_val := ex_reg_div_val && io.dpath.div_rdy mem_reg_div_val := ex_reg_div_val && io.dpath.div_rdy
@ -571,6 +574,13 @@ class Control(implicit conf: RocketConfiguration) extends Component
(mem_reg_mem_val && io.dmem.xcpt.pf.ld, UFix(10)), (mem_reg_mem_val && io.dmem.xcpt.pf.ld, UFix(10)),
(mem_reg_mem_val && io.dmem.xcpt.pf.st, UFix(11)))) (mem_reg_mem_val && io.dmem.xcpt.pf.st, UFix(11))))
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen)
val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem
val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem
wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !wb_reg_replay_next wb_reg_xcpt := mem_xcpt && !take_pc_wb && !wb_reg_replay_next
when (mem_xcpt) { wb_reg_cause := mem_cause } when (mem_xcpt) { wb_reg_cause := mem_cause }
@ -581,6 +591,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
wb_reg_fp_wen := Bool(false); wb_reg_fp_wen := Bool(false);
wb_reg_eret := Bool(false); wb_reg_eret := Bool(false);
wb_reg_flush_inst := Bool(false); wb_reg_flush_inst := Bool(false);
wb_reg_mem_val := Bool(false)
wb_reg_div_mul_val := Bool(false); wb_reg_div_mul_val := Bool(false);
wb_reg_fp_val := Bool(false) wb_reg_fp_val := Bool(false)
wb_reg_replay_next := Bool(false) wb_reg_replay_next := Bool(false)
@ -592,77 +603,45 @@ class Control(implicit conf: RocketConfiguration) extends Component
wb_reg_fp_wen := mem_reg_fp_wen; wb_reg_fp_wen := mem_reg_fp_wen;
wb_reg_eret := mem_reg_eret && !mem_reg_replay wb_reg_eret := mem_reg_eret && !mem_reg_replay
wb_reg_flush_inst := mem_reg_flush_inst; wb_reg_flush_inst := mem_reg_flush_inst;
wb_reg_mem_val := mem_reg_mem_val
wb_reg_div_mul_val := mem_reg_div_val || mem_reg_mul_val wb_reg_div_mul_val := mem_reg_div_val || mem_reg_mul_val
wb_reg_fp_val := mem_reg_fp_val wb_reg_fp_val := mem_reg_fp_val
wb_reg_replay_next := mem_reg_replay_next wb_reg_replay_next := mem_reg_replay_next
} }
val sboard = new rocketCtrlSboard(32, 3, 2); val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || vec_replay || io.dpath.pcr_replay
sboard.io.r(0).addr := id_raddr2.toUFix;
sboard.io.r(1).addr := id_raddr1.toUFix;
sboard.io.r(2).addr := id_waddr.toUFix;
// scoreboard set (for D$ misses, div, mul) class Scoreboard
sboard.io.w(0).en := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen {
sboard.io.w(0).data := Bool(true) val r = Reg(resetVal = Bits(0))
sboard.io.w(0).addr := io.dpath.wb_waddr var next = r
var ens = Bool(false)
sboard.io.w(1).en := io.dpath.sboard_clr def apply(addr: UFix) = r(addr)
sboard.io.w(1).data := Bool(false) def set(en: Bool, addr: UFix): Unit = update(en, next | mask(en, addr))
sboard.io.w(1).addr := io.dpath.sboard_clra def clear(en: Bool, addr: UFix): Unit = update(en, next & ~mask(en, addr))
private def mask(en: Bool, addr: UFix) = Mux(en, UFix(1) << addr, UFix(0))
val id_stall_raddr2 = id_renx2.toBool && sboard.io.r(0).data private def update(en: Bool, update: Bits) = {
val id_stall_raddr1 = id_renx1.toBool && sboard.io.r(1).data next = update
val id_stall_waddr = id_wen.toBool && sboard.io.r(2).data ens = ens || en
when (ens) { r := next }
var id_stall_fpu = Bool(false) }
if (HAVE_FPU) {
val fp_sboard = new rocketCtrlSboard(32, 4, 3);
fp_sboard.io.r(0).addr := id_raddr1.toUFix
fp_sboard.io.r(1).addr := id_raddr2.toUFix
fp_sboard.io.r(2).addr := id_raddr3.toUFix
fp_sboard.io.r(3).addr := id_waddr.toUFix
fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set
fp_sboard.io.w(0).data := Bool(true)
fp_sboard.io.w(0).addr := io.dpath.fp_sboard_wb_waddr
fp_sboard.io.w(1).en := io.dpath.fp_sboard_clr
fp_sboard.io.w(1).data := Bool(false)
fp_sboard.io.w(1).addr := io.dpath.fp_sboard_clra
fp_sboard.io.w(2).en := io.fpu.sboard_clr
fp_sboard.io.w(2).data := Bool(false)
fp_sboard.io.w(2).addr := io.fpu.sboard_clra
id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.r(0).data ||
io.fpu.dec.ren2 && fp_sboard.io.r(1).data ||
io.fpu.dec.ren3 && fp_sboard.io.r(2).data ||
io.fpu.dec.wen && fp_sboard.io.r(3).data
} }
// replay inst in ex stage val sboard = new Scoreboard
val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst || sboard.set(wb_reg_div_mul_val || wb_dcache_miss && io.dpath.wb_wen, io.dpath.wb_waddr)
ex_reg_mem_val && !io.dmem.req.ready || sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr)
ex_reg_div_val && !io.dpath.div_rdy ||
ex_reg_mul_val && !io.dpath.mul_rdy ||
mem_reg_replay_next
ctrl_killx := take_pc_wb || replay_ex
// replay inst in mem stage val id_stall_fpu = if (HAVE_FPU) {
val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val val fp_sboard = new Scoreboard
val dmem_kill_mem = mem_reg_valid && io.dmem.resp.bits.nack fp_sboard.set(wb_dcache_miss && wb_reg_fp_wen && !replay_wb || io.fpu.sboard_set, io.dpath.wb_waddr)
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || fpu_kill_mem fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
val killm_common = mem_reg_wen && mem_ll_wb || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || dmem_kill_mem || fpu_kill_mem
mem_reg_replay := replay_ex && !take_pc_wb;
wb_reg_replay := replay_mem && !take_pc_wb
val replay_wb = wb_reg_replay || vec_replay || io.dpath.pcr_replay
io.fpu.dec.ren1 && fp_sboard(id_raddr1) ||
io.fpu.dec.ren2 && fp_sboard(id_raddr2) ||
io.fpu.dec.ren3 && fp_sboard(id_raddr3) ||
io.fpu.dec.wen && fp_sboard(id_waddr)
} else Bool(false)
// write cause to PCR on an exception // write cause to PCR on an exception
io.dpath.exception := wb_reg_xcpt io.dpath.exception := wb_reg_xcpt
@ -671,7 +650,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
io.dpath.vec_irq_aux_wen := wb_reg_xcpt && wb_reg_cause >= UFix(24) && wb_reg_cause < UFix(32) io.dpath.vec_irq_aux_wen := wb_reg_xcpt && wb_reg_cause >= UFix(24) && wb_reg_cause < UFix(32)
// control transfer from ex/wb // control transfer from ex/wb
take_pc_wb := wb_reg_replay || vec_replay || wb_reg_xcpt || wb_reg_eret take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_eret
take_pc := take_pc_ex || take_pc_wb; take_pc := take_pc_ex || take_pc_wb;
io.dpath.sel_pc := io.dpath.sel_pc :=
@ -700,7 +679,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val) fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage. // stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
val mem_mem_cmd_bh = val mem_mem_cmd_bh = if (conf.fastLoadByte) Bool(false) else
(mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) || (mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU) (mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU)
val data_hazard_mem = mem_reg_wen && val data_hazard_mem = mem_reg_wen &&
@ -718,20 +697,24 @@ class Control(implicit conf: RocketConfiguration) extends Component
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_reg_wen && val data_hazard_wb = wb_reg_wen &&
(id_raddr1 != UFix(0) && id_renx1 && id_raddr1 === io.dpath.wb_waddr || (id_raddr1 != UFix(0) && id_renx1 && (id_raddr1 === io.dpath.wb_waddr) ||
id_raddr2 != UFix(0) && id_renx2 && id_raddr2 === io.dpath.wb_waddr || id_raddr2 != UFix(0) && id_renx2 && (id_raddr2 === io.dpath.wb_waddr) ||
id_waddr != UFix(0) && id_wen && id_waddr === io.dpath.wb_waddr) id_waddr != UFix(0) && id_wen && (id_waddr === io.dpath.wb_waddr))
val fp_data_hazard_wb = wb_reg_fp_wen && val fp_data_hazard_wb = wb_reg_fp_wen &&
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr || (io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr) io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) || val id_wb_hazard = data_hazard_wb && (wb_dcache_miss || wb_reg_div_mul_val) ||
fp_data_hazard_wb && (wb_reg_dcache_miss || wb_reg_fp_val) fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
val id_sboard_hazard =
(id_raddr1 != UFix(0) && id_renx1 && sboard(id_raddr1) ||
id_raddr2 != UFix(0) && id_renx2 && sboard(id_raddr2) ||
id_waddr != UFix(0) && id_wen && sboard(id_waddr))
val ctrl_stalld = val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
id_fp_val && id_stall_fpu || id_fp_val && id_stall_fpu ||
id_mem_val && !io.dmem.req.ready || id_mem_val && !io.dmem.req.ready ||
vec_stalld vec_stalld
@ -742,6 +725,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
io.imem.invalidate := wb_reg_flush_inst io.imem.invalidate := wb_reg_flush_inst
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
io.dpath.wb_load := wb_reg_mem_val && io.dpath.wb_wen
io.dpath.ren2 := id_renx2.toBool; io.dpath.ren2 := id_renx2.toBool;
io.dpath.ren1 := id_renx1.toBool; io.dpath.ren1 := id_renx1.toBool;
io.dpath.sel_alu2 := id_sel_alu2.toUFix io.dpath.sel_alu2 := id_sel_alu2.toUFix
@ -758,13 +742,14 @@ class Control(implicit conf: RocketConfiguration) extends Component
io.dpath.ex_jalr := ex_reg_jalr io.dpath.ex_jalr := ex_reg_jalr
io.dpath.ex_wen := ex_reg_wen; io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen; io.dpath.mem_wen := mem_reg_wen;
io.dpath.wb_wen := wb_reg_wen; io.dpath.wb_wen := wb_reg_wen && !replay_wb
io.dpath.wb_valid := wb_reg_valid && !vec_replay io.dpath.wb_valid := wb_reg_valid && !replay_wb
io.dpath.sel_wa := id_sel_wa.toBool; io.dpath.sel_wa := id_sel_wa.toBool;
io.dpath.sel_wb := id_sel_wb.toUFix io.dpath.sel_wb := id_sel_wb.toUFix
io.dpath.pcr := wb_reg_pcr.toUFix io.dpath.pcr := wb_reg_pcr.toUFix
io.dpath.wb_eret := wb_reg_eret; io.dpath.eret := wb_reg_eret
io.dpath.ex_mem_type := ex_reg_mem_type io.dpath.ex_mem_type := ex_reg_mem_type
io.dpath.ex_br_type := ex_reg_br_type
io.fpu.valid := !ctrl_killd && id_fp_val io.fpu.valid := !ctrl_killd && id_fp_val
io.fpu.killx := ctrl_killx io.fpu.killx := ctrl_killx

32
rocket/src/main/scala/ctrl_util.scala
View File

@ -1,32 +0,0 @@
package rocket
import Chisel._
import Node._
class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
{
class read_port extends Bundle {
val addr = UFix(INPUT, log2Up(entries))
val data = Bool(OUTPUT)
}
class write_port extends Bundle {
val en = Bool(INPUT)
val addr = UFix(INPUT, log2Up(entries))
val data = Bool(INPUT)
}
val io = new Bundle {
val r = Vec(nread) { new read_port() }
val w = Vec(nwrite) { new write_port() }
}
val busybits = Reg(resetVal = Bits(0, entries))
val wmasks = (0 until nwrite).map(i => Fill(entries, io.w(i).en) & (UFix(1) << io.w(i).addr))
val wdatas = (0 until nwrite).map(i => Mux(io.w(i).data, wmasks(i), UFix(0)))
var next = busybits & ~wmasks.reduceLeft(_|_) | wdatas.reduceLeft(_|_)
busybits := next
for (i <- 0 until nread)
io.r(i).data := busybits(io.r(i).addr)
}

148
rocket/src/main/scala/dpath.scala
View File

@ -4,6 +4,7 @@ import Chisel._
import Node._ import Node._
import Constants._ import Constants._
import Instructions._ import Instructions._
import Util._
import hwacha._ import hwacha._
class Datapath(implicit conf: RocketConfiguration) extends Component class Datapath(implicit conf: RocketConfiguration) extends Component
@ -21,13 +22,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN) val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN)
} }
val pcr = new rocketDpathPCR();
val ex_pcr = pcr.io.r.data;
val alu = new ALU
val ex_alu_out = alu.io.out;
val ex_alu_adder_out = alu.io.adder_out;
// execute definitions // execute definitions
val ex_reg_pc = Reg() { UFix() }; val ex_reg_pc = Reg() { UFix() };
val ex_reg_inst = Reg() { Bits() }; val ex_reg_inst = Reg() { Bits() };
@ -59,7 +53,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
val wb_reg_rs2 = Reg() { Bits() }; val wb_reg_rs2 = Reg() { Bits() };
val wb_reg_waddr = Reg() { UFix() } val wb_reg_waddr = Reg() { UFix() }
val wb_reg_wdata = Reg() { Bits() } val wb_reg_wdata = Reg() { Bits() }
val wb_reg_dmem_wdata = Reg() { Bits() }
val wb_reg_vec_waddr = Reg() { UFix() } val wb_reg_vec_waddr = Reg() { UFix() }
val wb_reg_vec_wdata = Reg() { Bits() } val wb_reg_vec_wdata = Reg() { Bits() }
val wb_reg_raddr1 = Reg() { UFix() }; val wb_reg_raddr1 = Reg() { UFix() };
@ -67,25 +60,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
val wb_reg_ll_wb = Reg(resetVal = Bool(false)); val wb_reg_ll_wb = Reg(resetVal = Bool(false));
val wb_wdata = Bits(); val wb_wdata = Bits();
val dmem_resp_replay = Bool()
val r_dmem_resp_replay = Reg(resetVal = Bool(false));
val r_dmem_fp_replay = Reg(resetVal = Bool(false));
val r_dmem_resp_waddr = Reg() { UFix() };
val ex_pc_plus4 = ex_reg_pc + UFix(4);
val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2(VADDR_BITS-1,0), Bits(0,1)).toUFix
val ex_ea_sign = Mux(ex_alu_adder_out(VADDR_BITS-1), ~ex_alu_adder_out(63,VADDR_BITS) === UFix(0), ex_alu_adder_out(63,VADDR_BITS) != UFix(0))
val ex_effective_address = Cat(ex_ea_sign, ex_alu_adder_out(VADDR_BITS-1,0)).toUFix
// hook up I$
io.imem.req.bits.currentpc := ex_reg_pc
io.imem.req.bits.pc :=
Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target),
Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec).toUFix,
wb_reg_pc))) // PC_WB
// instruction decode stage // instruction decode stage
val id_inst = io.imem.resp.bits.data val id_inst = io.imem.resp.bits.data
val id_pc = io.imem.resp.bits.pc val id_pc = io.imem.resp.bits.pc
@ -159,17 +133,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
when (io.ctrl.ren2) { ex_reg_rs2 := id_rs2 } when (io.ctrl.ren2) { ex_reg_rs2 := id_rs2 }
} }
val ex_rs1 = Mux(Reg(id_rs1_dmem_bypass), wb_reg_dmem_wdata, ex_reg_rs1) val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data
val ex_rs2 = Mux(Reg(id_rs2_dmem_bypass), wb_reg_dmem_wdata, ex_reg_rs2) val ex_rs1 = Mux(Reg(id_rs1_dmem_bypass), dmem_resp_data, ex_reg_rs1)
val ex_op2 = Mux(Reg(id_op2_dmem_bypass), wb_reg_dmem_wdata, ex_reg_op2) val ex_rs2 = Mux(Reg(id_rs2_dmem_bypass), dmem_resp_data, ex_reg_rs2)
val ex_op2 = Mux(Reg(id_op2_dmem_bypass), dmem_resp_data, ex_reg_op2)
val alu = new ALU
alu.io.dw := ex_reg_ctrl_fn_dw; alu.io.dw := ex_reg_ctrl_fn_dw;
alu.io.fn := ex_reg_ctrl_fn_alu; alu.io.fn := ex_reg_ctrl_fn_alu;
alu.io.in2 := ex_op2.toUFix alu.io.in2 := ex_op2.toUFix
alu.io.in1 := ex_rs1.toUFix alu.io.in1 := ex_rs1.toUFix
io.fpu.fromint_data := ex_rs1
// divider // divider
val div = new rocketDivider(earlyOut = true) val div = new rocketDivider(earlyOut = true)
div.io.req.valid := io.ctrl.div_val div.io.req.valid := io.ctrl.div_val
@ -178,7 +152,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
div.io.req.bits.in1 := ex_op2 div.io.req.bits.in1 := ex_op2
div.io.req_tag := ex_reg_waddr div.io.req_tag := ex_reg_waddr
div.io.req_kill := io.ctrl.div_kill div.io.req_kill := io.ctrl.div_kill
div.io.resp_rdy := !dmem_resp_replay div.io.resp_rdy := Bool(true)
io.ctrl.div_rdy := div.io.req.ready io.ctrl.div_rdy := div.io.req.ready
io.ctrl.div_result_val := div.io.resp_val io.ctrl.div_result_val := div.io.resp_val
@ -197,11 +171,23 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
mul_io.req.bits.in1 := ex_op2 mul_io.req.bits.in1 := ex_op2
mul_io.req_tag := ex_reg_waddr mul_io.req_tag := ex_reg_waddr
mul_io.req_kill := io.ctrl.mul_kill mul_io.req_kill := io.ctrl.mul_kill
mul_io.resp_rdy := !dmem_resp_replay && !div.io.resp_val mul_io.resp_rdy := Bool(true)
io.ctrl.mul_rdy := mul_io.req.ready io.ctrl.mul_rdy := mul_io.req.ready
io.ctrl.mul_result_val := mul_io.resp_val io.ctrl.mul_result_val := mul_io.resp_val
io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection & bypass control io.fpu.fromint_data := ex_rs1
io.ctrl.ex_waddr := ex_reg_waddr
def vaSign(a0: Bits, ea: Bits) = {
// efficient means to compress 64-bit VA into VADDR_BITS+1 bits
// (VA is bad if VA(VADDR_BITS) != VA(VADDR_BITS-1))
val a = a0 >> VADDR_BITS-1
val e = ea(VADDR_BITS,VADDR_BITS-1)
Mux(a === UFix(0) || a === UFix(1), e != UFix(0),
Mux(a === Fix(-1) || a === Fix(-2), e === Fix(-1),
Bool(false)))
}
val ex_effective_address = Cat(vaSign(ex_rs1, alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUFix
// D$ request interface (registered inside D$ module) // D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module // other signals (req_val, req_rdy) connect to control module
@ -211,14 +197,13 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
require(io.dmem.req.bits.tag.getWidth >= 6) require(io.dmem.req.bits.tag.getWidth >= 6)
// processor control regfile read // processor control regfile read
val pcr = new rocketDpathPCR()
pcr.io.r.en := io.ctrl.pcr != PCR_N pcr.io.r.en := io.ctrl.pcr != PCR_N
pcr.io.r.addr := wb_reg_raddr1 pcr.io.r.addr := wb_reg_raddr1
pcr.io.host <> io.host pcr.io.host <> io.host
pcr.io <> io.ctrl
io.ctrl.irq_timer := pcr.io.irq_timer; pcr.io.pc := wb_reg_pc
io.ctrl.irq_ipi := pcr.io.irq_ipi;
io.ctrl.status := pcr.io.status;
io.ctrl.pcr_replay := pcr.io.replay io.ctrl.pcr_replay := pcr.io.replay
io.ptw.ptbr := pcr.io.ptbr io.ptw.ptbr := pcr.io.ptbr
@ -227,11 +212,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
// branch resolution logic // branch resolution logic
io.ctrl.jalr_eq := ex_reg_rs1 === id_pc.toFix && ex_reg_op2(id_imm_small.getWidth-1,0) === UFix(0) io.ctrl.jalr_eq := ex_reg_rs1 === id_pc.toFix && ex_reg_op2(id_imm_small.getWidth-1,0) === UFix(0)
io.ctrl.br_eq := (ex_rs1 === ex_rs2) io.ctrl.ex_br_taken :=
io.ctrl.br_ltu := (ex_rs1.toUFix < ex_rs2.toUFix) Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2,
io.ctrl.br_lt := Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2,
(~(ex_rs1(63) ^ ex_rs2(63)) & io.ctrl.br_ltu | Mux(io.ctrl.ex_br_type === BR_LT, ex_rs1.toFix < ex_rs2.toFix,
ex_rs1(63) & ~ex_rs2(63)).toBool Mux(io.ctrl.ex_br_type === BR_GE, ex_rs1.toFix >= ex_rs2.toFix,
Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs1 < ex_rs2,
Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
io.ctrl.ex_br_type === BR_J))))))
val ex_pc_plus4 = ex_reg_pc + UFix(4)
val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2(VADDR_BITS-1,0), Bits(0,1)).toUFix
// time stamp counter // time stamp counter
val tsc_reg = Reg(resetVal = UFix(0,64)); val tsc_reg = Reg(resetVal = UFix(0,64));
@ -245,7 +236,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4.toFix, Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4.toFix,
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg, Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg, Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
ex_alu_out))).toBits // WB_ALU alu.io.out))).toBits // WB_ALU
// memory stage // memory stage
mem_reg_kill := ex_reg_kill mem_reg_kill := ex_reg_kill
@ -262,23 +253,29 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
// for load/use hazard detection (load byte/halfword) // for load/use hazard detection (load byte/halfword)
io.ctrl.mem_waddr := mem_reg_waddr; io.ctrl.mem_waddr := mem_reg_waddr;
// 32/64 bit load handling (moved to earlier in file)
// writeback arbitration // writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool
val dmem_resp_waddr = io.dmem.resp.bits.tag.toUFix >> UFix(1) val dmem_resp_waddr = io.dmem.resp.bits.tag.toUFix >> UFix(1)
dmem_resp_replay := io.dmem.resp.bits.replay && dmem_resp_xpu; val dmem_resp_replay = io.dmem.resp.bits.replay && dmem_resp_xpu
r_dmem_resp_replay := dmem_resp_replay
r_dmem_resp_waddr := dmem_resp_waddr
r_dmem_fp_replay := io.dmem.resp.bits.replay && dmem_resp_fpu;
val mem_ll_waddr = Mux(dmem_resp_replay, dmem_resp_waddr, val mem_ll_wdata = Bits()
Mux(div.io.resp_val, div.io.resp_tag, mem_ll_wdata := mul_io.resp_bits
mul_io.resp_tag)) io.ctrl.mem_ll_waddr := mul_io.resp_tag
val mem_ll_wdata = Mux(div.io.resp_val, div.io.resp_bits, io.ctrl.mem_ll_wb := mul_io.resp_val
mul_io.resp_bits) when (div.io.resp_val) {
val mem_ll_wb = dmem_resp_replay || div.io.resp_val || mul_io.resp_val mul_io.resp_rdy := Bool(false)
mem_ll_wdata := div.io.resp_bits
io.ctrl.mem_ll_waddr := div.io.resp_tag
io.ctrl.mem_ll_wb := Bool(true)
}
when (dmem_resp_replay) {
mul_io.resp_rdy := Bool(false)
div.io.resp_rdy := Bool(false)
mem_ll_wdata := io.dmem.resp.bits.data_subword
io.ctrl.mem_ll_waddr := dmem_resp_waddr
io.ctrl.mem_ll_wb := Bool(true)
}
io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu
io.fpu.dmem_resp_data := io.dmem.resp.bits.data io.fpu.dmem_resp_data := io.dmem.resp.bits.data
@ -286,9 +283,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
io.fpu.dmem_resp_tag := dmem_resp_waddr io.fpu.dmem_resp_tag := dmem_resp_waddr
// writeback stage // writeback stage
when (io.ctrl.mem_load) {
wb_reg_dmem_wdata := io.dmem.resp.bits.data
}
when (!mem_reg_kill) { when (!mem_reg_kill) {
wb_reg_pc := mem_reg_pc wb_reg_pc := mem_reg_pc
wb_reg_inst := mem_reg_inst wb_reg_inst := mem_reg_inst
@ -300,15 +294,12 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
wb_reg_waddr := mem_reg_waddr wb_reg_waddr := mem_reg_waddr
wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata) wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
} }
wb_reg_ll_wb := mem_ll_wb wb_reg_ll_wb := io.ctrl.mem_ll_wb
when (mem_ll_wb) { when (io.ctrl.mem_ll_wb) {
wb_reg_waddr := mem_ll_waddr wb_reg_waddr := io.ctrl.mem_ll_waddr
wb_reg_wdata := mem_ll_wdata wb_reg_wdata := mem_ll_wdata
} }
// regfile write
val wb_src_dmem = Reg(io.ctrl.mem_load) && io.ctrl.wb_valid || r_dmem_resp_replay
if (HAVE_VEC) if (HAVE_VEC)
{ {
// vector datapath // vector datapath
@ -333,7 +324,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
wb_wdata := wb_wdata :=
Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl), Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),
Mux(wb_src_dmem, io.dmem.resp.bits.data_subword, Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
wb_reg_wdata)) wb_reg_wdata))
} }
else else
@ -344,7 +335,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
pcr.io.vec_nfregs := UFix(0) pcr.io.vec_nfregs := UFix(0)
wb_wdata := wb_wdata :=
Mux(wb_src_dmem, io.dmem.resp.bits.data_subword, Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
wb_reg_wdata) wb_reg_wdata)
} }
@ -355,14 +346,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
when (rf_wen) { writeRF(rf_waddr, rf_wdata) } when (rf_wen) { writeRF(rf_waddr, rf_wdata) }
io.ctrl.wb_waddr := wb_reg_waddr io.ctrl.wb_waddr := wb_reg_waddr
io.ctrl.mem_wb := dmem_resp_replay;
// scoreboard clear (for div/mul and D$ load miss writebacks) // scoreboard clear (for div/mul and D$ load miss writebacks)
io.ctrl.sboard_clr := mem_ll_wb io.ctrl.fp_sboard_clr := io.dmem.resp.bits.replay && dmem_resp_fpu
io.ctrl.sboard_clra := mem_ll_waddr io.ctrl.fp_sboard_clra := dmem_resp_waddr
io.ctrl.fp_sboard_clr := r_dmem_fp_replay
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr
io.ctrl.fp_sboard_wb_waddr := Reg(mem_reg_waddr)
// processor control regfile write // processor control regfile write
pcr.io.w.addr := wb_reg_raddr1 pcr.io.w.addr := wb_reg_raddr1
@ -371,10 +358,11 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
Mux(io.ctrl.pcr === PCR_C, pcr.io.r.data & ~wb_reg_wdata, Mux(io.ctrl.pcr === PCR_C, pcr.io.r.data & ~wb_reg_wdata,
wb_reg_wdata)) wb_reg_wdata))
pcr.io.eret := io.ctrl.wb_eret; // hook up I$
pcr.io.exception := io.ctrl.exception; io.imem.req.bits.currentpc := ex_reg_pc
pcr.io.cause := io.ctrl.cause; io.imem.req.bits.pc :=
pcr.io.pc := wb_reg_pc; Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen; Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target),
pcr.io.vec_irq_aux_wen := io.ctrl.vec_irq_aux_wen Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec).toUFix,
wb_reg_pc))) // PC_WB
} }

15
rocket/src/main/scala/fpu.scala
View File

@ -183,7 +183,7 @@ object RegEn
when (en) { r := data } when (en) { r := data }
r r
} }
def apply[T <: Bits](data: T, en: Bool, resetVal: Bool) = { def apply[T <: Bits](data: T, en: Bool, resetVal: T) = {
val r = Reg(resetVal = resetVal) { data.clone } val r = Reg(resetVal = resetVal) { data.clone }
when (en) { r := data } when (en) { r := data }
r r
@ -478,15 +478,10 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Component
val wb_ctrl = RegEn(mem_ctrl, mem_reg_valid) val wb_ctrl = RegEn(mem_ctrl, mem_reg_valid)
// load response // load response
val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false)) val load_wb = io.dpath.dmem_resp_val
val load_wb_single = Reg() { Bool() } val load_wb_single = io.dpath.dmem_resp_type === MT_W
val load_wb_data = Reg() { Bits(width = 64) } // XXX WTF why doesn't bit width inference work for the regfile?! val load_wb_data = io.dpath.dmem_resp_data
val load_wb_tag = Reg() { UFix() } val load_wb_tag = io.dpath.dmem_resp_tag
when (io.dpath.dmem_resp_val) {
load_wb_single := io.dpath.dmem_resp_type === MT_W || io.dpath.dmem_resp_type === MT_WU
load_wb_data := io.dpath.dmem_resp_data
load_wb_tag := io.dpath.dmem_resp_tag
}
val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9) val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9)
val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12) val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
val load_wb_data_recoded = Mux(load_wb_single, Cat(Fix(-1, 32), rec_s), rec_d) val load_wb_data_recoded = Mux(load_wb_single, Cat(Fix(-1, 32), rec_s), rec_d)

789
rocket/src/main/scala/nbdcache.scala
View File

File diff suppressed because it is too large Load Diff

2
rocket/src/main/scala/package.scala
View File

@ -18,7 +18,7 @@ object Constants extends
{ {
def HAVE_RVC = false def HAVE_RVC = false
def HAVE_FPU = true def HAVE_FPU = true
def HAVE_VEC = true def HAVE_VEC = false
val MAX_THREADS = val MAX_THREADS =
hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK

15
rocket/src/main/scala/ptw.scala
View File

@ -59,11 +59,10 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
req_addr := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), arb.io.out.bits(VPN_BITS-1,VPN_BITS-bitsPerLevel), UFix(0,3)) req_addr := Cat(io.dpath.ptbr(PADDR_BITS-1,PGIDX_BITS), arb.io.out.bits(VPN_BITS-1,VPN_BITS-bitsPerLevel), UFix(0,3))
} }
val dmem_resp_val = Reg(io.mem.resp.valid, resetVal = Bool(false)) when (io.mem.resp.valid) {
when (dmem_resp_val) { req_addr := Cat(io.mem.resp.bits.data(PADDR_BITS-1, PGIDX_BITS), vpn_idx, UFix(0,3)).toUFix
req_addr := Cat(io.mem.resp.bits.data_subword(PADDR_BITS-1, PGIDX_BITS), vpn_idx, UFix(0,3)).toUFix r_resp_perm := io.mem.resp.bits.data(9,4);
r_resp_perm := io.mem.resp.bits.data_subword(9,4); r_resp_ppn := io.mem.resp.bits.data(PADDR_BITS-1, PGIDX_BITS);
r_resp_ppn := io.mem.resp.bits.data_subword(PADDR_BITS-1, PGIDX_BITS);
} }
io.mem.req.valid := state === s_req io.mem.req.valid := state === s_req
@ -76,8 +75,8 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
val resp_val = state === s_done || state === s_error val resp_val = state === s_done || state === s_error
val resp_err = state === s_error || state === s_wait val resp_err = state === s_error || state === s_wait
val resp_ptd = io.mem.resp.bits.data_subword(1,0) === Bits(1) val resp_ptd = io.mem.resp.bits.data(1,0) === Bits(1)
val resp_pte = io.mem.resp.bits.data_subword(1,0) === Bits(2) val resp_pte = io.mem.resp.bits.data(1,0) === Bits(2)
val resp_ppns = (0 until levels-1).map(i => Cat(r_resp_ppn(PPN_BITS-1, VPN_BITS-bitsPerLevel*(i+1)), r_req_vpn(VPN_BITS-1-bitsPerLevel*(i+1), 0))) val resp_ppns = (0 until levels-1).map(i => Cat(r_resp_ppn(PPN_BITS-1, VPN_BITS-bitsPerLevel*(i+1)), r_req_vpn(VPN_BITS-1-bitsPerLevel*(i+1), 0)))
val resp_ppn = (0 until levels-1).foldRight(r_resp_ppn)((i,j) => Mux(count === UFix(i), resp_ppns(i), j)) val resp_ppn = (0 until levels-1).foldRight(r_resp_ppn)((i,j) => Mux(count === UFix(i), resp_ppns(i), j))
@ -109,7 +108,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
when (io.mem.resp.bits.nack) { when (io.mem.resp.bits.nack) {
state := s_req state := s_req
} }
when (dmem_resp_val) { when (io.mem.resp.valid) {
when (resp_pte) { // page table entry when (resp_pte) { // page table entry
state := s_done state := s_done
} }

3
rocket/src/main/scala/tile.scala
View File

@ -6,7 +6,8 @@ import Constants._
import uncore._ import uncore._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached, case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
icache: ICacheConfig, dcache: DCacheConfig) icache: ICacheConfig, dcache: DCacheConfig,
fastLoadByte: Boolean = false)
{ {
val dcacheReqTagBits = 9 // enforce compliance with require() val dcacheReqTagBits = 9 // enforce compliance with require()
} }