riscv/rocket-chip
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new D$ with better QoR and AMO pipelining

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Vector unit is disabled because nack handling needs to be fixed.
This commit is contained in:
Andrew Waterman
2012-11-16 02:39:33 -08:00
parent a90a1790a5
commit 8dce89703a
11 changed files with 738 additions and 956 deletions
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15
rocket/src/main/scala/fpu.scala
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@ -183,7 +183,7 @@ object RegEn
when (en) { r := data }
r
}
def apply[T <: Bits](data: T, en: Bool, resetVal: Bool) = {
def apply[T <: Bits](data: T, en: Bool, resetVal: T) = {
val r = Reg(resetVal = resetVal) { data.clone }
when (en) { r := data }
r
@ -478,15 +478,10 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Component
val wb_ctrl = RegEn(mem_ctrl, mem_reg_valid)
// load response
val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false))
val load_wb_single = Reg() { Bool() }
val load_wb_data = Reg() { Bits(width = 64) } // XXX WTF why doesn't bit width inference work for the regfile?!
val load_wb_tag = Reg() { UFix() }
when (io.dpath.dmem_resp_val) {
load_wb_single := io.dpath.dmem_resp_type === MT_W || io.dpath.dmem_resp_type === MT_WU
load_wb_data := io.dpath.dmem_resp_data
load_wb_tag := io.dpath.dmem_resp_tag
}
val load_wb = io.dpath.dmem_resp_val
val load_wb_single = io.dpath.dmem_resp_type === MT_W
val load_wb_data = io.dpath.dmem_resp_data
val load_wb_tag = io.dpath.dmem_resp_tag
val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9)
val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
val load_wb_data_recoded = Mux(load_wb_single, Cat(Fix(-1, 32), rec_s), rec_d)