riscv/rocket-chip
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new D$ with better QoR and AMO pipelining

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Vector unit is disabled because nack handling needs to be fixed.
This commit is contained in:
Andrew Waterman
2012-11-16 02:39:33 -08:00
parent a90a1790a5
commit 8dce89703a
11 changed files with 738 additions and 956 deletions
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6
rocket/src/main/scala/core.scala
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@ -114,11 +114,11 @@ class Core(implicit conf: RocketConfiguration) extends Component
dmem(2).req.bits.data := Reg(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data)
vu.io.dmem_req.ready := dmem(2).req.ready
vu.io.dmem_resp.valid := Reg(dmem(2).resp.valid)
vu.io.dmem_resp.valid := dmem(2).resp.valid
vu.io.dmem_resp.bits.nack := dmem(2).resp.bits.nack
vu.io.dmem_resp.bits.data := dmem(2).resp.bits.data_subword
vu.io.dmem_resp.bits.tag := Reg(dmem(2).resp.bits.tag)
vu.io.dmem_resp.bits.typ := Reg(dmem(2).resp.bits.typ)
vu.io.dmem_resp.bits.tag := dmem(2).resp.bits.tag
vu.io.dmem_resp.bits.typ := dmem(2).resp.bits.typ
// share vector integer multiplier with rocket
dpath.io.vec_imul_req <> vu.io.cp_imul_req