tile: supply hartid from RocketTileParams

make WithNCores partial configs override rather than append more tiles

src/main/scala/coreplex/Configs.scala

@@ -45,7 +45,7 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
       icache = Some(ICacheParams(
         rowBits = site(SystemBusKey).beatBits,
         blockBytes = site(CacheBlockBytes))))
-    List.fill(n)(big) ++ up(RocketTilesKey, site)
+    List.tabulate(n)(i => big.copy(hartid = i))
   }
 })
 
@@ -67,7 +67,7 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
         nWays = 1,
         nTLBEntries = 4,
         blockBytes = site(CacheBlockBytes))))
-    List.fill(n)(small) ++ up(RocketTilesKey, site)
+    List.tabulate(n)(i => small.copy(hartid = i))
   }
 })
 
@@ -94,7 +94,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
           nWays = 1,
           nTLBEntries = 4,
           blockBytes = site(CacheBlockBytes))))
-    List.fill(n)(tiny) ++ up(RocketTilesKey, site)
+    List.tabulate(n)(i => tiny.copy(hartid = i))
   }
 })
 

src/main/scala/coreplex/RocketCoreplex.scala

@@ -24,6 +24,7 @@ trait HasRocketTiles extends HasSystemBus
   private val crossing = p(RocketCrossing)
   private val tileParams = p(RocketTilesKey)
   val nRocketTiles = tileParams.size
+  val hartIdList = tileParams.map(_.hartid)
 
   // Handle interrupts to be routed directly into each tile
   // TODO: figure out how to merge the localIntNodes and coreIntXbar below
@@ -34,8 +35,8 @@ trait HasRocketTiles extends HasSystemBus
 
   // Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
   // according to the specified type of clock crossing.
-  val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex
-  val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, tp), i) =>
+  val wiringTuple = localIntNodes.zip(tileParams)
+  val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case (lip, tp) =>
     val pWithExtra = p.alterPartial {
       case TileKey => tp
       case BuildRoCC => tp.rocc
@@ -44,19 +45,19 @@ trait HasRocketTiles extends HasSystemBus
 
     val wrapper = crossing match {
       case SynchronousCrossing(params) => {
-        val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra))
+        val wrapper = LazyModule(new SyncRocketTile(tp)(pWithExtra))
         sbus.fromSyncTiles(params, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
         FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toSyncSlaves(tp.name, tp.externalSlaveBuffers) }
         wrapper
       }
       case AsynchronousCrossing(depth, sync) => {
-        val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra))
+        val wrapper = LazyModule(new AsyncRocketTile(tp)(pWithExtra))
         sbus.fromAsyncTiles(depth, sync, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
         FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name, tp.externalSlaveBuffers) }
         wrapper
       }
       case RationalCrossing(direction) => {
-        val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra))
+        val wrapper = LazyModule(new RationalRocketTile(tp)(pWithExtra))
         sbus.fromRationalTiles(direction, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
         FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name, tp.externalSlaveBuffers) }
         wrapper
@@ -127,7 +128,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
   }
 
   // Default values for tile inputs; may be overriden in other traits
-  rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) =>
+  rocket_tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
     wire.clock := clock
     wire.reset := reset
     wire.hartid := UInt(i)

src/main/scala/system/Configs.scala

@@ -63,9 +63,6 @@ class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseCo
 class DualCoreConfig extends Config(
   new WithNBigCores(2) ++ new BaseConfig)
 
-class HeterogeneousDualCoreConfig extends Config(
-  new WithNSmallCores(1) ++ new WithNBigCores(1) ++ new BaseConfig)
-
 class TinyConfig extends Config(
   new WithNMemoryChannels(0) ++
   new WithStatelessBridge ++

src/main/scala/tile/RocketTile.scala

@@ -22,13 +22,14 @@ case class RocketTileParams(
     trace: Boolean = false,
     hcfOnUncorrectable: Boolean = false,
     name: Option[String] = Some("tile"),
+    hartid: Int = 0,
     externalMasterBuffers: Int = 0,
     externalSlaveBuffers: Int = 0) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
   
-class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
+class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
     with HasExternalInterrupts
     with HasLazyRoCC  // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
     with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
@@ -39,6 +40,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
   private def ofStr(x: String) = Seq(ResourceString(x))
   private def ofRef(x: Device) = Seq(ResourceReference(x.label))
 
+  val hartid = rocketParams.hartid
   val cpuDevice = new Device {
     def describe(resources: ResourceBindings): Description = {
       val block =  p(CacheBlockBytes)
@@ -179,8 +181,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
   ptw.io.requestor <> ptwPorts
 }
 
-abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
-  val rocket = LazyModule(new RocketTile(rtp, hartid))
+abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends LazyModule {
+  val rocket = LazyModule(new RocketTile(rtp))
   val asyncIntNode   : IntInwardNode
   val periphIntNode  : IntInwardNode
   val coreIntNode    : IntInwardNode
@@ -226,7 +228,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
   }
 }
 
-class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
+class SyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
   val masterNode = optionalMasterBuffer(rocket.masterNode)
   val slaveNode = optionalSlaveBuffer(rocket.slaveNode)
 
@@ -246,7 +248,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
   def outputInterruptXingLatency = 0
 }
 
-class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
+class AsyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
   val source = LazyModule(new TLAsyncCrossingSource)
   source.node :=* rocket.masterNode
   val masterNode = source.node
@@ -272,7 +274,7 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
   def outputInterruptXingLatency = 3
 }
 
-class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
+class RationalRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
   val source = LazyModule(new TLRationalCrossingSource)
   source.node :=* optionalMasterBuffer(rocket.masterNode)
   val masterNode = source.node