riscv/rocket-chip
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tile: supply hartid from RocketTileParams

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make WithNCores partial configs override rather than append more tiles
This commit is contained in:
Henry Cook
2017-10-05 00:31:53 -07:00
parent 45581e60f0
commit 8da7aabd51
4 changed files with 18 additions and 18 deletions
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6
src/main/scala/coreplex/Configs.scala
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@ -45,7 +45,7 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
icache = Some(ICacheParams(
rowBits = site(SystemBusKey).beatBits,
blockBytes = site(CacheBlockBytes))))
List.fill(n)(big) ++ up(RocketTilesKey, site)
List.tabulate(n)(i => big.copy(hartid = i))
}
})
@ -67,7 +67,7 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
nWays = 1,
nTLBEntries = 4,
blockBytes = site(CacheBlockBytes))))
List.fill(n)(small) ++ up(RocketTilesKey, site)
List.tabulate(n)(i => small.copy(hartid = i))
}
})
@ -94,7 +94,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
nWays = 1,
nTLBEntries = 4,
blockBytes = site(CacheBlockBytes))))
List.fill(n)(tiny) ++ up(RocketTilesKey, site)
List.tabulate(n)(i => tiny.copy(hartid = i))
}
})

13
src/main/scala/coreplex/RocketCoreplex.scala
View File

@ -24,6 +24,7 @@ trait HasRocketTiles extends HasSystemBus
private val crossing = p(RocketCrossing)
private val tileParams = p(RocketTilesKey)
val nRocketTiles = tileParams.size
val hartIdList = tileParams.map(_.hartid)
// Handle interrupts to be routed directly into each tile
// TODO: figure out how to merge the localIntNodes and coreIntXbar below
@ -34,8 +35,8 @@ trait HasRocketTiles extends HasSystemBus
// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
// according to the specified type of clock crossing.
val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex
val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, tp), i) =>
val wiringTuple = localIntNodes.zip(tileParams)
val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case (lip, tp) =>
val pWithExtra = p.alterPartial {
case TileKey => tp
case BuildRoCC => tp.rocc
@ -44,19 +45,19 @@ trait HasRocketTiles extends HasSystemBus
val wrapper = crossing match {
case SynchronousCrossing(params) => {
val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra))
val wrapper = LazyModule(new SyncRocketTile(tp)(pWithExtra))
sbus.fromSyncTiles(params, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toSyncSlaves(tp.name, tp.externalSlaveBuffers) }
wrapper
}
case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra))
val wrapper = LazyModule(new AsyncRocketTile(tp)(pWithExtra))
sbus.fromAsyncTiles(depth, sync, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name, tp.externalSlaveBuffers) }
wrapper
}
case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra))
val wrapper = LazyModule(new RationalRocketTile(tp)(pWithExtra))
sbus.fromRationalTiles(direction, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name, tp.externalSlaveBuffers) }
wrapper
@ -127,7 +128,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
}
// Default values for tile inputs; may be overriden in other traits
rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) =>
rocket_tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.clock := clock
wire.reset := reset
wire.hartid := UInt(i)