riscv/rocket-chip
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replace NASTIMasterIO and NASTISlaveIO with NASTIIO

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This commit is contained in:
Howard Mao 2015-09-24 16:59:13 -07:00
parent 4a85c5a510
commit 8d4d8680bf
4 changed files with 15 additions and 15 deletions
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2
junctions

@ -1 +1 @@
Subproject commit 3ad77802d200be7e1506a9add0faef3acf30bcd1 Subproject commit f64a12529b1bdc0456519fabdd1edb3b4db23b27

20
src/main/scala/RocketChip.scala
View File

@ -62,8 +62,8 @@ class TopIO extends BasicTopIO {
} }
class MultiChannelTopIO extends BasicTopIO with TopLevelParameters { class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
val mem = Vec(new NASTIMasterIO, nMemChannels) val mem = Vec(new NASTIIO, nMemChannels)
val mmio = new NASTIMasterIO val mmio = new NASTIIO
} }
/** Top-level module for the chip */ /** Top-level module for the chip */
@ -73,7 +73,7 @@ class Top extends Module with TopLevelParameters {
if(!params(UseZscale)) { if(!params(UseZscale)) {
val temp = Module(new MultiChannelTop) val temp = Module(new MultiChannelTop)
val arb = Module(new NASTIArbiter(nMemChannels)) val arb = Module(new NASTIArbiter(nMemChannels))
val conv = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits))) val conv = Module(new MemIONASTIIOConverter(params(CacheBlockOffsetBits)))
arb.io.master <> temp.io.mem arb.io.master <> temp.io.mem
conv.io.nasti <> arb.io.slave conv.io.nasti <> arb.io.slave
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd) io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
@ -127,12 +127,12 @@ class MultiChannelTop extends Module with TopLevelParameters {
class Uncore extends Module with TopLevelParameters { class Uncore extends Module with TopLevelParameters {
val io = new Bundle { val io = new Bundle {
val host = new HostIO val host = new HostIO
val mem = Vec(new NASTIMasterIO, nMemChannels) val mem = Vec(new NASTIIO, nMemChannels)
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif = Vec(new HTIFIO, nTiles).flip val htif = Vec(new HTIFIO, nTiles).flip
val mem_backup_ctrl = new MemBackupCtrlIO val mem_backup_ctrl = new MemBackupCtrlIO
val mmio = new NASTIMasterIO val mmio = new NASTIIO
} }
val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
@ -187,12 +187,12 @@ class OuterMemorySystem extends Module with TopLevelParameters {
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif_uncached = (new ClientUncachedTileLinkIO).flip val htif_uncached = (new ClientUncachedTileLinkIO).flip
val incoherent = Vec(Bool(), nTiles).asInput val incoherent = Vec(Bool(), nTiles).asInput
val mem = Vec(new NASTIMasterIO, nMemChannels) val mem = Vec(new NASTIIO, nMemChannels)
val mem_backup = new MemSerializedIO(htifW) val mem_backup = new MemSerializedIO(htifW)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val pcr = Vec(new SMIIO(64, 12), nTiles) val pcr = Vec(new SMIIO(64, 12), nTiles)
val scr = new SMIIO(64, scrAddrBits) val scr = new SMIIO(64, scrAddrBits)
val mmio = new NASTIMasterIO val mmio = new NASTIIO
} }
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory // Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
@ -232,7 +232,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
for ((bank, i) <- managerEndpoints.zipWithIndex) { for ((bank, i) <- managerEndpoints.zipWithIndex) {
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams) val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
val conv = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams) val conv = Module(new NASTIIOTileLinkIOConverter)(outerTLParams)
unwrap.io.in <> bank.outerTL unwrap.io.in <> bank.outerTL
conv.io.tl <> unwrap.io.out conv.io.tl <> unwrap.io.out
interconnect.io.masters(i) <> conv.io.nasti interconnect.io.masters(i) <> conv.io.nasti
@ -244,12 +244,12 @@ class OuterMemorySystem extends Module with TopLevelParameters {
for (i <- 0 until nTiles) { for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i" val csrName = s"conf:csr$i"
val csrPort = addrMap(csrName).port val csrPort = addrMap(csrName).port
val conv = Module(new SMIIONASTISlaveIOConverter(64, 12)) val conv = Module(new SMIIONASTIIOConverter(64, 12))
conv.io.nasti <> interconnect.io.slaves(csrPort) conv.io.nasti <> interconnect.io.slaves(csrPort)
io.pcr(i) <> conv.io.smi io.pcr(i) <> conv.io.smi
} }
val conv = Module(new SMIIONASTISlaveIOConverter(64, scrAddrBits)) val conv = Module(new SMIIONASTIIOConverter(64, scrAddrBits))
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port) conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
io.scr <> conv.io.smi io.scr <> conv.io.smi

6
src/main/scala/Vlsi.scala
View File

@ -15,8 +15,8 @@ class MemDessert extends Module {
object VLSIUtils { object VLSIUtils {
def doOuterMemorySystemSerdes( def doOuterMemorySystemSerdes(
llcs: Seq[NASTIMasterIO], llcs: Seq[NASTIIO],
mems: Seq[NASTIMasterIO], mems: Seq[NASTIIO],
backup: MemSerializedIO, backup: MemSerializedIO,
en: Bool, en: Bool,
nMemChannels: Int, nMemChannels: Int,
@ -24,7 +24,7 @@ object VLSIUtils {
blockOffsetBits: Int) { blockOffsetBits: Int) {
val arb = Module(new NASTIArbiter(nMemChannels)) val arb = Module(new NASTIArbiter(nMemChannels))
val conv = Module(new MemIONASTISlaveIOConverter(blockOffsetBits)) val conv = Module(new MemIONASTIIOConverter(blockOffsetBits))
val mem_serdes = Module(new MemSerdes(htifWidth)) val mem_serdes = Module(new MemSerdes(htifWidth))
conv.io.nasti <> arb.io.slave conv.io.nasti <> arb.io.slave

2
uncore

@ -1 +1 @@
Subproject commit d6895713cf4c0fcc53a3507f0c376716be8b0dce Subproject commit 356c759af0bff468e93911ace2aa18c162f7e77c