riscv/rocket-chip
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replace NASTIMasterIO and NASTISlaveIO with NASTIIO

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This commit is contained in:
Howard Mao
2015-09-24 16:59:13 -07:00
parent 4a85c5a510
commit 8d4d8680bf
4 changed files with 15 additions and 15 deletions
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6
src/main/scala/Vlsi.scala
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@ -15,8 +15,8 @@ class MemDessert extends Module {
object VLSIUtils {
def doOuterMemorySystemSerdes(
llcs: Seq[NASTIMasterIO],
mems: Seq[NASTIMasterIO],
llcs: Seq[NASTIIO],
mems: Seq[NASTIIO],
backup: MemSerializedIO,
en: Bool,
nMemChannels: Int,
@ -24,7 +24,7 @@ object VLSIUtils {
blockOffsetBits: Int) {
val arb = Module(new NASTIArbiter(nMemChannels))
val conv = Module(new MemIONASTISlaveIOConverter(blockOffsetBits))
val conv = Module(new MemIONASTIIOConverter(blockOffsetBits))
val mem_serdes = Module(new MemSerdes(htifWidth))
conv.io.nasti <> arb.io.slave