Moved updating global history from fetch to decode.

- No longer update global history in fetch stage.
   - Only update global history when instruction is a branch.
   - Does allow for the possibility of back-to-back branches to see
     slightly different histories on subsequent executions.

rocket/src/main/scala/icache.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import Instructions._
 
 case object NITLBEntries extends Field[Int]
 case object ECCCode extends Field[Option[Code]]
@@ -44,7 +45,7 @@ class Frontend extends FrontendModule
     val cpu = new CPUFrontendIO().flip
     val mem = new UncachedTileLinkIO
   }
-  
+
   val btb = Module(new BTB)
   val icache = Module(new ICache)
   val tlb = Module(new TLB(params(NITLBEntries)))
@@ -85,10 +86,12 @@ class Frontend extends FrontendModule
     s2_valid := Bool(false)
   }
 
-  btb.io.req.valid := io.cpu.resp.fire()
-  btb.io.req.bits := s1_pc & SInt(-coreInstBytes)
+  btb.io.req := s1_pc & SInt(-coreInstBytes)
   btb.io.update := io.cpu.btb_update
   btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
+  btb.io.decode.valid := io.cpu.resp.valid && DecodeIsBr(io.cpu.resp.bits.data)
+  btb.io.decode.bits.taken := Reg(next=btb.io.resp.bits.taken)
+
 
   tlb.io.ptw <> io.cpu.ptw
   tlb.io.req.valid := !stall && !icmiss
@@ -285,3 +288,21 @@ class ICache extends FrontendModule
     }
   }
 }
+
+object DecodeIsBr {
+  def apply(inst: Bits): Bool = {
+    val signal = DecodeLogic(inst.toUInt,   List(N),
+            Array(//JAL     -> List(Y),
+                  //JALR    -> List(Y),
+                  BEQ     -> List(Y),
+                  BNE     -> List(Y),
+                  BGE     -> List(Y),
+                  BGEU    -> List(Y),
+                  BLT     -> List(Y),
+                  BLTU    -> List(Y)))
+
+    val (is_br: Bool) :: Nil = signal
+    is_br
+  }
+}
+