fix IdMapper and TL -> NASTI converter
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@ -40,7 +40,7 @@ class IdMapper(val inIdBits: Int, val outIdBits: Int,
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val out_id_free = Reg(init = Vec.fill(nOutXacts){Bool(true)})
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val out_id_free = Reg(init = Vec.fill(nOutXacts){Bool(true)})
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val next_out_id = PriorityEncoder(out_id_free)
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val next_out_id = PriorityEncoder(out_id_free)
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val id_mapping = Reg(Vec(nInXacts, UInt(0, outIdBits)))
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val id_mapping = Reg(Vec(nInXacts, UInt(0, outIdBits)))
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val id_valid = Reg(init = Vec.fill(nOutXacts){Bool(false)})
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val id_valid = Reg(init = Vec.fill(nInXacts){Bool(false)})
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val req_fire = io.req.valid && io.req.ready
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val req_fire = io.req.valid && io.req.ready
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when (req_fire) {
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when (req_fire) {
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@ -236,7 +236,8 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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id = put_id_mapper.io.req.out_id,
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id = put_id_mapper.io.req.out_id,
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data = io.tl.acquire.bits.data,
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data = io.tl.acquire.bits.data,
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strb = Some(io.tl.acquire.bits.wmask()),
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strb = Some(io.tl.acquire.bits.wmask()),
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last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
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last = Mux(w_inflight,
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tl_cnt_out === UInt(tlDataBeats - 1), !is_multibeat))
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io.tl.acquire.ready := Mux(has_data,
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io.tl.acquire.ready := Mux(has_data,
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put_helper.fire(put_valid),
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put_helper.fire(put_valid),
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