add LR/SC support

rocket/src/main/scala/ctrl.scala

@@ -127,6 +127,11 @@ object XDecode extends DecodeConstants
     AMOMINU_D-> List(xpr64,N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XA_MINU,MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
     AMOMAX_D->  List(xpr64,N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XA_MAX, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
     AMOMAXU_D-> List(xpr64,N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XA_MAXU,MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
+
+    LR_W->      List(Y,    N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XLR,    MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
+    LR_D->      List(xpr64,N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XLR,    MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
+    SC_W->      List(Y,    N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XSC,    MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
+    SC_D->      List(xpr64,N,N,BR_N,  N,Y,Y,A2_ZERO, DW_XPR,FN_ADD,   Y,M_XSC,    MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
                                         
     LUI->       List(Y,    N,N,BR_N,  N,N,N,A2_LTYPE,DW_XPR,FN_OP2,   N,M_X,      MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
     ADDI->      List(Y,    N,N,BR_N,  N,N,Y,A2_ITYPE,DW_XPR,FN_ADD,   N,M_X,      MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
@@ -383,7 +388,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
   val mem_reg_replay_next     = Reg(resetVal = Bool(false))
   val mem_reg_pcr             = Reg(resetVal = PCR.N)
   val mem_reg_cause           = Reg(){UFix()}
-  val mem_reg_mem_type        = Reg(){Bits()}
+  val mem_reg_slow_bypass     = Reg(){Bool()}
 
   val wb_reg_valid           = Reg(resetVal = Bool(false))
   val wb_reg_pcr             = Reg(resetVal = PCR.N)
@@ -516,8 +521,9 @@ class Control(implicit conf: RocketConfiguration) extends Component
                      ex_reg_div_mul_val && !io.dpath.div_mul_rdy ||
                      mem_reg_replay_next
   ctrl_killx := take_pc_wb || replay_ex
-
   val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === io.dpath.ex_br_taken)
+  // detect 2-cycle load-use delay for LB/LH/SC
+  val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type)
 
   val (ex_xcpt, ex_cause) = checkExceptions(List(
     (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
@@ -552,7 +558,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
     mem_reg_fp_val := ex_reg_fp_val
     mem_reg_vec_val := ex_reg_vec_val
     mem_reg_replay_next := ex_reg_replay_next
-    mem_reg_mem_type := ex_reg_mem_type
+    mem_reg_slow_bypass := ex_slow_bypass
     mem_reg_xcpt := ex_xcpt
   }
 
@@ -667,9 +673,8 @@ class Control(implicit conf: RocketConfiguration) extends Component
     
   // stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage.
   val mem_mem_cmd_bh =
-    if (!conf.fastLoadWord) Bool(true)
+    if (conf.fastLoadWord) Bool(!conf.fastLoadByte) && mem_reg_slow_bypass
-    else if (conf.fastLoadByte) Bool(false)
+    else Bool(true)
-    else AVec(MT_B, MT_BU, MT_H, MT_HU) contains mem_reg_mem_type
   val data_hazard_mem = mem_reg_wen &&
     (id_raddr1 != UFix(0) && id_renx1 && id_raddr1 === io.dpath.mem_waddr ||
      id_raddr2 != UFix(0) && id_renx2 && id_raddr2 === io.dpath.mem_waddr ||

rocket/src/main/scala/dpath.scala

@@ -200,6 +200,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
 
   io.ptw.ptbr := pcr.io.ptbr
   io.ptw.invalidate := pcr.io.ptbr_wen
+  io.ptw.eret := io.ctrl.eret
   io.ptw.status := pcr.io.status
   
 	// branch resolution logic

rocket/src/main/scala/instructions.scala

@@ -88,6 +88,10 @@ object Instructions
   val AMOMAX_D   = Bits("b?????_?????_?????_0000101011_0101011",32);
   val AMOMINU_D  = Bits("b?????_?????_?????_0000110011_0101011",32);
   val AMOMAXU_D  = Bits("b?????_?????_?????_0000111011_0101011",32);
+  val LR_W       = Bits("b?????_?????_00000_1000000010_0101011",32);
+  val LR_D       = Bits("b?????_?????_00000_1000000011_0101011",32);
+  val SC_W       = Bits("b?????_?????_?????_1000001010_0101011",32);
+  val SC_D       = Bits("b?????_?????_?????_1000001011_0101011",32);
   val FENCE_I    = Bits("b?????_?????_????????????_001_0101111",32);
   val FENCE      = Bits("b?????_?????_????????????_010_0101111",32);
   val SYSCALL    = Bits("b00000_00000_00000_0000000000_1110111",32);

rocket/src/main/scala/nbdcache.scala

@@ -869,6 +869,17 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
   val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en)){Bits()})
   val s2_hit = s2_tag_match && conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state)
 
+  // load-reserved/store-conditional
+  val s2_lr_valid = Reg(resetVal = Bool(false))
+  val s2_lr_addr = Reg{UFix()}
+  val s2_lr_addr_match = s2_lr_addr === (s2_req.addr >> conf.offbits)
+  when (s2_valid_masked && s2_req.cmd === M_XLR) {
+    s2_lr_valid := true
+    s2_lr_addr := s2_req.addr >> conf.offbits
+  }
+  when (prober.io.mshr_req.valid && s2_lr_addr_match) { s2_lr_valid := false }
+  when (io.cpu.ptw.eret) { s2_lr_valid := false }
+
   val s2_data = Vec(conf.ways){Bits(width = conf.bitsperrow)}
   for (w <- 0 until conf.ways) {
     val regs = Vec(conf.wordsperrow){Reg{Bits(width = conf.encdatabits)}}
@@ -1015,13 +1026,13 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
     io.cpu.req.ready := Bool(false)
   }
 
-  val s2_read = isRead(s2_req.cmd)
+  val s2_read = isRead(s2_req.cmd) || s2_req.cmd === M_XSC
   io.cpu.resp.valid  := s2_read && (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
   io.cpu.resp.bits.nack := s2_valid && s2_nack
   io.cpu.resp.bits := s2_req
   io.cpu.resp.bits.replay := s2_replay && s2_read
   io.cpu.resp.bits.data := loadgen.word
-  io.cpu.resp.bits.data_subword := loadgen.byte
+  io.cpu.resp.bits.data_subword := Mux(s2_req.cmd === M_XSC, !s2_lr_addr_match, loadgen.byte)
   io.cpu.resp.bits.store_data := s2_req.data
   
   io.mem.grant_ack <> mshr.io.mem_finish

rocket/src/main/scala/ptw.scala

@@ -15,11 +15,13 @@ class TLBPTWIO extends Bundle {
 
   val status = new Status().asInput
   val invalidate = Bool(INPUT)
+  val eret = Bool(INPUT)
 }
 
 class DatapathPTWIO extends Bundle {
   val ptbr = UFix(INPUT, PADDR_BITS)
   val invalidate = Bool(INPUT)
+  val eret = Bool(INPUT)
   val status = new Status().asInput
 }
 
@@ -82,6 +84,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
     io.requestor(i).resp.bits.perm := r_pte(9,4)
     io.requestor(i).resp.bits.ppn := resp_ppn.toUFix
     io.requestor(i).invalidate := io.dpath.invalidate
+    io.requestor(i).eret := io.dpath.eret
     io.requestor(i).status := io.dpath.status
   }