add LR/SC support

rocket/src/main/scala/ptw.scala

@@ -15,11 +15,13 @@ class TLBPTWIO extends Bundle {
 
   val status = new Status().asInput
   val invalidate = Bool(INPUT)
+  val eret = Bool(INPUT)
 }
 
 class DatapathPTWIO extends Bundle {
   val ptbr = UFix(INPUT, PADDR_BITS)
   val invalidate = Bool(INPUT)
+  val eret = Bool(INPUT)
   val status = new Status().asInput
 }
 
@@ -82,6 +84,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
     io.requestor(i).resp.bits.perm := r_pte(9,4)
     io.requestor(i).resp.bits.ppn := resp_ppn.toUFix
     io.requestor(i).invalidate := io.dpath.invalidate
+    io.requestor(i).eret := io.dpath.eret
     io.requestor(i).status := io.dpath.status
   }