From 8cb250cfe6708962275e766c3dabc2ca95a2f54e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <aswaterman@gmail.com>
Date: Thu, 8 Jun 2017 01:50:00 -0700
Subject: [PATCH] Fix FMUL sign, again (#789)

---
 src/main/scala/tile/FPU.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
index 3b3f62fc..3bd28b4c 100644
--- a/src/main/scala/tile/FPU.scala
+++ b/src/main/scala/tile/FPU.scala
@@ -552,7 +552,7 @@ class FPUFMAPipe(val latency: Int, val t: FType)(implicit p: Parameters) extends
   val in = Reg(new FPInput)
   when (io.in.valid) {
     val one = UInt(1) << (t.sig + t.exp - 1)
-    val zero = UInt(1) << (t.sig + t.exp)
+    val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (UInt(1) << (t.sig + t.exp))
     val cmd_fma = io.in.bits.ren3
     val cmd_addsub = io.in.bits.swap23
     in := io.in.bits