riscv/rocket-chip
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Merge branch 'master' into hwacha-port

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Mostly Stable version that is passing tests
This commit is contained in:
Stephen Twigg
2014-02-04 17:20:28 -08:00
parent 8062888fb9 fc52840ce2
commit 8c96e27ca6
10 changed files with 104 additions and 89 deletions
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4
Makefrag
View File

@@ -2,7 +2,7 @@
MODEL := Top
CXX := g++
CXXFLAGS := -O2
CXXFLAGS := -O1
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
@@ -111,6 +111,8 @@ asm_p_tests = \
rv64uf-p-fmin \
rv64uf-p-fmadd \
rv64uf-p-structural \
rv64si-p-coreid \
rv64si-p-csr \
rv64si-pm-ipi \
rv64ui-pm-lrsc \

2
chisel

Submodule chisel updated: 8db5030aee...b88b521f07

30
emulator/Makefile
View File

@@ -10,7 +10,7 @@ CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include
CXXSRCS := emulator disasm mm mm_dramsim2
CXXFLAGS := $(CXXFLAGS) -I$(base_dir)/csrc -I$(base_dir)/dramsim2
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
@@ -18,22 +18,30 @@ DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
generated-src/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
generated-src-debug/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
generated-src-debug/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
$(MODEL).o: %.o: generated-src/%.cpp
$(MODEL).o: %.o: generated-src/%.h
$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp))
$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp)) -o $@
$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.h
$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp))
$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp)) -o $@
$(wildcard generated-src/*.o): %.o: %.cpp generated-src/$(MODEL).h
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.cpp
$(wildcard generated-src-debug/*.o): %.o: %.cpp generated-src-debug/$(MODEL).h
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).cpp
$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).h
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).cpp
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).h
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
emulator: $(OBJS) libdramsim.a
@@ -52,6 +60,8 @@ test:
# Run assembly tests and benchmarks
#--------------------------------------------------------------------
MAX_CYCLES=30000000
%.hex:
$(MAKE) -C $(dir $@) $(notdir $@)
@@ -74,15 +84,15 @@ output:
mkdir -p $@
output/%.run: output/%.hex emulator
./emulator +dramsim +max-cycles=30000000 +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
./emulator +dramsim +max-cycles=$(MAX_CYCLES) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
output/%.out: output/%.hex emulator
./emulator +dramsim +max-cycles=30000000 +verbose +coremap-random +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
./emulator +dramsim +max-cycles=$(MAX_CYCLES) +verbose +coremap-random +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
output/%.vpd: output/%.hex emulator-debug
rm -rf $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null &
./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
./emulator-debug +dramsim +max-cycles=$(MAX_CYCLES) +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;

2
riscv-tests

Submodule riscv-tests updated: a481561500...f6d8b4850e

2
riscv-tools

Submodule riscv-tools updated: ace38a2b39...76441991a8

2
rocket

Submodule rocket updated: 674a3ed523...d631234253

16
src/main/scala/RocketChip.scala
View File

@@ -83,7 +83,7 @@ class ReferenceChipBackend extends VerilogBackend
transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
}
class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
val io = new Bundle {
@@ -101,10 +101,10 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
val mem_serdes = Module(new MemSerdes(htif_width))
require(clientEndpoints.length == ln.nClients)
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
val net = Module(new ReferenceChipCrossbarNetwork)
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
@@ -145,7 +145,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{
implicit val tl = conf.tl
val io = new Bundle {
@@ -158,7 +158,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup_en = Bool(INPUT)
}
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val outmemsys = Module(new OuterMemorySystem(htif_width))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif
@@ -246,7 +246,7 @@ class Top extends Module {
else new MICoherence
}
implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
@@ -265,7 +265,7 @@ class Top extends Module {
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
val uncore = Module(new Uncore(HTIF_WIDTH))
for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i)

16
src/main/scala/fpga.scala
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@@ -5,7 +5,7 @@ import Node._
import uncore._
import rocket._
class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
val io = new Bundle {
@@ -15,11 +15,11 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
val mem = new ioMem
}
require(clientEndpoints.length == ln.nClients)
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
val net = Module(new ReferenceChipCrossbarNetwork)
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
@@ -35,7 +35,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
conv.io.mem.resp <> Queue(io.mem.resp)
}
class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{
implicit val (tl, ln) = (conf.tl, conf.tl.ln)
val io = new Bundle {
@@ -46,7 +46,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
}
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif
@@ -85,7 +85,7 @@ class FPGATop extends Module {
val ntiles = 1
val nbanks = 1
val nmshrs = 2
implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1)
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64)
@@ -100,7 +100,7 @@ class FPGATop extends Module {
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new FPGAUncore(htif_width, tileList))
val uncore = Module(new FPGAUncore(htif_width))
for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i)

117
src/main/scala/network.scala
View File

@@ -3,25 +3,26 @@ package referencechip
import Chisel._
import uncore._
import scala.reflect._
import scala.reflect.runtime.universe._
object TileLinkHeaderAppender {
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
def apply[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](in: PairedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
val shim = Module(new TileLinkHeaderAppender(in.meta.bits.payload, in.data.bits.payload, clientId, nBanks, addrConvert))
shim.io.in <> in
shim.io.out
}
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = {
val shim = Module(new TileLinkHeaderAppender(in.bits.payload.clone, new AcquireData, clientId, nBanks, addrConvert))
shim.io.in.meta <> in
shim.io.out.meta
}
}
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module {
class TileLinkHeaderAppender[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module {
implicit val ln = conf.ln
val io = new Bundle {
val in = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip
val out = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType))
val in = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip
val out = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType))
}
val meta_q = Queue(io.in.meta)
@@ -93,11 +94,21 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfi
io.mem.req_data <> mem_data_q.io.deq
}
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) {
class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) {
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}}))
val io = new Bundle {
val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
val masters = Vec.fill(ln.nMasters){new TileLinkIO}
}
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
// Actually instantiate the particular networks required for TileLink
val acqNet = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, (acq: PhysicalNetworkIO[Acquire]) => co.messageHasData(acq.payload)))
val relNet = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, (rel: PhysicalNetworkIO[Release]) => co.messageHasData(rel.payload)))
val probeNet = Module(new BasicCrossbar(new Probe))
val grantNet = Module(new BasicCrossbar(new Grant))
val ackNet = Module(new BasicCrossbar(new GrantAck))
// Aliases for the various network IO bundle types
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
@@ -163,61 +174,53 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
phys_in.valid := Bool(false)
}
// Use reflection to determine whether a particular endpoint should be
// hooked up as an [input/output] for a FIFO nework that is transmiitting
// [client/master]-sourced messages.
def doFIFOHookup[S <: CoherenceAgentRole: ClassTag, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
// Is end's type a subtype of S, the agent type associated with inputs?
if(classTag[S].runtimeClass.isInstance(end))
doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
else
doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
def doFIFOHookup[T <: Data](isEndpointSourceOfMessage: Boolean, physIn: FBCIO[T], physOut: FBCIO[T], logIO: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
if(isEndpointSourceOfMessage) doFIFOInputHookup(physIn, physOut, logIO, inShim)
else doFIFOOutputHookup(physIn, physOut, logIO, outShim)
}
def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim)
def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim)
// Use reflection to determine whether a particular endpoint should be
// hooked up as an [input/output] for a Paired nework that is transmiitting
// [client/master]-sourced messages.
def doPairedDataHookup[S <: CoherenceAgentRole : ClassTag, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
// Is end's type a subtype of S, the agent type associated with inputs?
if(classTag[S].runtimeClass.isInstance(end)) {
doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
} else {
doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
//Hookup all instances of a particular subbundle of
def doFIFOHookups[T <: Data: TypeTag](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => FLNIO[T]) = {
typeTag[T].tpe match{
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
}
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
}
case _ => require(false, "Unknown message sourcing.")
}
}
def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim)
def doPairedDataHookup[T <: Data, R <: Data](isEndpointSourceOfMessage: Boolean, physIn: PBCIO[T,R], physOut: PBCIO[T,R], logIO: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
if(isEndpointSourceOfMessage) {
doFIFOInputHookup[T](physIn.meta, physOut.meta, logIO.meta, inShim)
doFIFOInputHookup[R](physIn.data, physOut.data, logIO.data, inShimD)
} else {
doFIFOOutputHookup[T](physIn.meta, physOut.meta, logIO.meta, outShim)
doFIFOOutputHookup[R](physIn.data, physOut.data, logIO.data, outShimD)
}
}
def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim)
def doPairedDataHookups[T <: Data: TypeTag, R <: Data](physIO: PairedCrossbarIO[T,R], getLogIO: TileLinkIO => PLNIO[T,R]) = {
typeTag[T].tpe match{
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) }
io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) }
}
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) }
io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) }
}
case _ => require(false, "Unknown message sourcing.")
}
}
// Actually instantiate the particular networks required for TileLink
def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
val acq_net = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, acqHasData _))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload)
val rel_net = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, relHasData _))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
val probe_net = Module(new BasicCrossbar(new Probe))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
val grant_net = Module(new BasicCrossbar(new Grant))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
val ack_net = Module(new BasicCrossbar(new GrantAck))
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
doPairedDataHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
doPairedDataHookups(relNet.io, (tl: TileLinkIO) => tl.release)
doFIFOHookups(probeNet.io, (tl: TileLinkIO) => tl.probe)
doFIFOHookups(grantNet.io, (tl: TileLinkIO) => tl.grant)
doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack)
}

2
uncore

Submodule uncore updated: a58265755f...f2a0b435fd