riscv/rocket-chip
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Support SCR address generation with __OFFSET at the end

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This commit is contained in:
Palmer Dabbelt 2016-02-25 21:57:37 -08:00
parent 640204b221
commit 8c73d10fe1
2 changed files with 4 additions and 4 deletions
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6
csrc/htif_emulator.h
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@ -24,17 +24,17 @@ class htif_emulator_t : public htif_pthread_t
void set_clock_divisor(int divisor, int hold_cycles) void set_clock_divisor(int divisor, int hold_cycles)
{ {
#ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR #ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET
/* We only want to write the HTIF clock divisor SCR on targets where it /* We only want to write the HTIF clock divisor SCR on targets where it
* actually exists (there isn't one on the FPGA, for example). */ * actually exists (there isn't one on the FPGA, for example). */
write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16); write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET, divisor | hold_cycles << 16);
#endif #endif
} }
void start() void start()
{ {
set_clock_divisor(5, 2); set_clock_divisor(5, 2);
write_cr(-1, UNCORE_SCR__MEMORY_CHANNEL_MUX_SELECT, memory_channel_mux_select); write_cr(-1, UNCORE_SCR__MEMORY_CHANNEL_MUX_SELECT__OFFSET, memory_channel_mux_select);
htif_pthread_t::start(); htif_pthread_t::start();
} }

2
uncore

@ -1 +1 @@
Subproject commit e8d3518437c7cfd6544937441c9c2e758a8e48fc Subproject commit 42549fd7cfa86075a82cbbd10adf6d41b3dcad67