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Bump chisel and firrtl (#1232)

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* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
This commit is contained in:
Jack Koenig
2018-03-01 15:19:12 -08:00
committed by GitHub
parent 20a8876856
commit 8c6e745653
10 changed files with 10 additions and 22 deletions
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2
src/main/scala/tilelink/RegisterRouter.scala
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@ -143,7 +143,7 @@ class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
implicit val p = arg.p
}
class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
class TLRegBundle[P](val params: P, val arg: TLRegBundleArg) extends TLRegBundleBase(arg)
class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap