riscv/rocket-chip
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make sure CSR/SCR data width matches xLen

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This commit is contained in:
Howard Mao 2015-09-25 12:07:03 -07:00
parent d1f2d40a90
commit 8c4ac0f4f3
2 changed files with 8 additions and 6 deletions
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7
uncore/src/main/scala/htif.scala
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@ -10,6 +10,7 @@ case object HTIFWidth extends Field[Int]
case object HTIFNSCR extends Field[Int] case object HTIFNSCR extends Field[Int]
case object HTIFOffsetBits extends Field[Int] case object HTIFOffsetBits extends Field[Int]
case object HTIFNCores extends Field[Int] case object HTIFNCores extends Field[Int]
case object HTIFSCRDataBits extends Field[Int]
abstract trait HTIFParameters extends UsesParameters { abstract trait HTIFParameters extends UsesParameters {
val dataBits = params(TLDataBits) val dataBits = params(TLDataBits)
@ -17,6 +18,8 @@ abstract trait HTIFParameters extends UsesParameters {
val w = params(HTIFWidth) val w = params(HTIFWidth)
val nSCR = params(HTIFNSCR) val nSCR = params(HTIFNSCR)
val scrAddrBits = log2Up(nSCR) val scrAddrBits = log2Up(nSCR)
val scrDataBits = params(HTIFSCRDataBits)
val scrDataBytes = scrDataBits / 8
val offsetBits = params(HTIFOffsetBits) val offsetBits = params(HTIFOffsetBits)
val nCores = params(HTIFNCores) val nCores = params(HTIFNCores)
} }
@ -35,7 +38,7 @@ class HostIO extends HTIFBundle
class HTIFIO extends HTIFBundle { class HTIFIO extends HTIFBundle {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores)) val id = UInt(INPUT, log2Up(nCores))
val pcr = new SMIIO(64, 12).flip val pcr = new SMIIO(scrDataBits, 12).flip
val ipi_req = Decoupled(Bits(width = log2Up(nCores))) val ipi_req = Decoupled(Bits(width = log2Up(nCores)))
val ipi_rep = Decoupled(Bool()).flip val ipi_rep = Decoupled(Bool()).flip
val debug_stats_pcr = Bool(OUTPUT) val debug_stats_pcr = Bool(OUTPUT)
@ -48,7 +51,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val host = new HostIO val host = new HostIO
val cpu = Vec(new HTIFIO, nCores).flip val cpu = Vec(new HTIFIO, nCores).flip
val mem = new ClientUncachedTileLinkIO val mem = new ClientUncachedTileLinkIO
val scr = new SMIIO(64, scrAddrBits) val scr = new SMIIO(scrDataBits, scrAddrBits)
} }
io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_) io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)

7
uncore/src/main/scala/rtc.scala
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@ -1,16 +1,15 @@
package uncore package uncore
import Chisel._ import Chisel._
import junctions.{NASTIIO, NASTIAddrHashMap, SMIIO} import junctions._
class RTC(pcr_MTIME: Int) extends Module { class RTC(pcr_MTIME: Int) extends Module with HTIFParameters {
val io = new NASTIIO val io = new NASTIIO
private val nCores = params(HTIFNCores)
private val addrMap = params(NASTIAddrHashMap) private val addrMap = params(NASTIAddrHashMap)
val addrTable = Vec.tabulate(nCores) { i => val addrTable = Vec.tabulate(nCores) { i =>
UInt(addrMap(s"conf:csr$i").start + pcr_MTIME * 8) UInt(addrMap(s"conf:csr$i").start + pcr_MTIME * scrDataBytes)
} }
val rtc = Reg(init=UInt(0,64)) val rtc = Reg(init=UInt(0,64))