riscv/rocket-chip
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tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer

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This commit is contained in:
Wesley W. Terpstra 2017-05-17 06:47:21 -07:00
parent 1f2236cdb3
commit 8c3736e0dc
2 changed files with 0 additions and 27 deletions
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1
src/main/scala/rocketchip/Configs.scala
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@ -28,7 +28,6 @@ class BasePlatformConfig extends Config((site, here, up) => {
case RTCPeriod => 1000 // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz case RTCPeriod => 1000 // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz
// TileLink connection parameters // TileLink connection parameters
case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args))) case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
case TLFuzzReadyValid => false
case TLCombinationalCheck => false case TLCombinationalCheck => false
//Memory Parameters //Memory Parameters
case NExtTopInterrupts => 2 case NExtTopInterrupts => 2

26
src/main/scala/uncore/tilelink2/Nodes.scala
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@ -10,7 +10,6 @@ import scala.collection.mutable.ListBuffer
import util.RationalDirection import util.RationalDirection
case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]] case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]]
case object TLFuzzReadyValid extends Field[Boolean]
case object TLCombinationalCheck extends Field[Boolean] case object TLCombinationalCheck extends Field[Boolean]
object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
@ -41,31 +40,6 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
bi.d.ready := bo.d.ready && bi.d.valid bi.d.ready := bo.d.ready && bi.d.valid
bo.e.ready := bi.e.ready && bo.e.valid bo.e.ready := bi.e.ready && bo.e.valid
} }
if (p(TLCombinationalCheck)) {
// Randomly stall the transfers
val allow = LFSRNoiseMaker(5)
bi.a.valid := bo.a.valid && allow(0)
bo.a.ready := bi.a.ready && allow(0)
bo.b.valid := bi.b.valid && allow(1)
bi.b.ready := bo.b.ready && allow(1)
bi.c.valid := bo.c.valid && allow(2)
bo.c.ready := bi.c.ready && allow(2)
bo.d.valid := bi.d.valid && allow(3)
bi.d.ready := bo.d.ready && allow(3)
bi.e.valid := bo.e.valid && allow(4)
bo.e.ready := bi.e.ready && allow(4)
// Inject garbage whenever not valid
val bits_a = bo.a.bits.fromBits(LFSRNoiseMaker(bo.a.bits.asUInt.getWidth))
val bits_b = bi.b.bits.fromBits(LFSRNoiseMaker(bi.b.bits.asUInt.getWidth))
val bits_c = bo.c.bits.fromBits(LFSRNoiseMaker(bo.c.bits.asUInt.getWidth))
val bits_d = bi.d.bits.fromBits(LFSRNoiseMaker(bi.d.bits.asUInt.getWidth))
val bits_e = bo.e.bits.fromBits(LFSRNoiseMaker(bo.e.bits.asUInt.getWidth))
when (!bi.a.valid) { bi.a.bits := bits_a }
when (!bo.b.valid) { bo.b.bits := bits_b }
when (!bi.c.valid) { bi.c.bits := bits_c }
when (!bo.d.valid) { bo.d.bits := bits_d }
when (!bi.e.valid) { bi.e.bits := bits_e }
}
} }
}) })
} }