1
0

separate out common functionality

This commit is contained in:
Howard Mao 2015-11-18 20:53:19 -08:00
parent 10f4c6c71c
commit 8bc90ab9bd
3 changed files with 70 additions and 52 deletions

View File

@ -31,41 +31,6 @@ trait HasGeneratorParams {
require(startAddress % genWordBytes == 0)
}
class Timer(initCount: Int) extends Module {
val io = new Bundle {
val start = Bool(INPUT)
val stop = Bool(INPUT)
val timeout = Bool(OUTPUT)
}
val countdown = Reg(UInt(width = log2Up(initCount)))
val active = Reg(init = Bool(false))
when (io.start) {
countdown := UInt(initCount - 1)
active := Bool(true)
}
when (io.stop) {
active := Bool(false)
}
when (active) {
countdown := countdown - UInt(1)
}
io.timeout := countdown === UInt(0)
}
object Timer {
def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
val timer = Module(new Timer(initCount))
timer.io.start := start
timer.io.stop := stop
timer.io.timeout
}
}
class UncachedTileLinkGenerator(id: Int)
(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {

View File

@ -3,6 +3,7 @@ package groundtest
import Chisel._
import rocket._
import uncore._
import junctions.SMIIO
import scala.util.Random
import cde.Parameters
@ -33,6 +34,33 @@ class DummyCache(implicit val p: Parameters) extends Module
}
}
class CSRHandler(implicit val p: Parameters) extends Module {
private val csrDataBits = 64
private val csrAddrBits = 12
val io = new Bundle {
val finished = Bool(INPUT)
val csr = new SMIIO(csrDataBits, csrAddrBits).flip
}
val csr_resp_valid = Reg(Bool()) // Don't reset
val csr_resp_data = Reg(UInt(width = csrDataBits))
io.csr.req.ready := Bool(true)
io.csr.resp.valid := csr_resp_valid
io.csr.resp.bits := csr_resp_data
when (io.csr.req.fire()) {
val req = io.csr.req.bits
csr_resp_valid := Bool(true)
csr_resp_data := Mux(req.addr === UInt(CSRs.mtohost), io.finished, req.data)
}
when (io.csr.resp.fire()) {
csr_resp_valid := Bool(false)
}
}
class GeneratorTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) extends Tile(resetSignal)(p)
with HasGeneratorParams {
@ -83,21 +111,8 @@ class GeneratorTile(id: Int, resetSignal: Bool)
}
val all_done = gen_finished.reduce(_ && _)
val csr_resp_valid = Reg(Bool()) // Don't reset
val csr_resp_data = Reg(io.host.csr.resp.bits)
io.host.csr.req.ready := Bool(true)
io.host.csr.resp.valid := csr_resp_valid
io.host.csr.resp.bits := csr_resp_data
when (io.host.csr.req.fire()) {
val req = io.host.csr.req.bits
csr_resp_valid := Bool(true)
csr_resp_data := Mux(req.addr === UInt(CSRs.mtohost), all_done, req.data)
}
when (io.host.csr.resp.fire()) {
csr_resp_valid := Bool(false)
}
val csr = Module(new CSRHandler)
csr.io.finished := all_done
csr.io.csr <> io.host.csr
}

View File

@ -0,0 +1,38 @@
package groundtest
import Chisel._
class Timer(initCount: Int) extends Module {
val io = new Bundle {
val start = Bool(INPUT)
val stop = Bool(INPUT)
val timeout = Bool(OUTPUT)
}
val countdown = Reg(UInt(width = log2Up(initCount)))
val active = Reg(init = Bool(false))
when (io.start) {
countdown := UInt(initCount - 1)
active := Bool(true)
}
when (io.stop) {
active := Bool(false)
}
when (active) {
countdown := countdown - UInt(1)
}
io.timeout := countdown === UInt(0)
}
object Timer {
def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
val timer = Module(new Timer(initCount))
timer.io.start := start
timer.io.stop := stop
timer.io.timeout
}
}