From 8bb397a1b9b3d069aea7fd6845322f64045d7b10 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 8 Mar 2018 01:59:04 -0500 Subject: [PATCH] Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge --- riscv-tools | 2 +- vsim/Makefrag | 4 ++-- vsim/Makefrag-verilog | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/riscv-tools b/riscv-tools index 98682995..3190b9c2 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 98682995dc4a1ab8777ff45ba673cf2658e54ae2 +Subproject commit 3190b9c21ecb5a845614937aadf56988d05a0e2f diff --git a/vsim/Makefrag b/vsim/Makefrag index 36716d77..281df88f 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -80,5 +80,5 @@ $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) #-------------------------------------------------------------------- seed = $(shell date +%s) -exec_simv = $(simv) -q +ntb_random_seed_automatic -exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic +exec_simv = $(simv) +permissive -q +ntb_random_seed_automatic +permissive-off +exec_simv_debug = $(simv_debug) +permissive -q +ntb_random_seed_automatic +permissive-off diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 82db9f7a..46ab0356 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -28,19 +28,19 @@ $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf .PRECIOUS: $(output_dir)/%.vpd $(output_dir)/%.run: $(output_dir)/% $(simv) - cd $(sim_dir) && $(exec_simv) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] + cd $(sim_dir) && $(exec_simv) +permissive +max-cycles=$(timeout_cycles) +permissive-off $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] $(output_dir)/%.out: $(output_dir)/% $(simv) - cd $(sim_dir) && $(exec_simv) +verbose +max-cycles=$(timeout_cycles) $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] + cd $(sim_dir) && $(exec_simv) +permissive +verbose +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] $(output_dir)/%.vcd: $(output_dir)/% $(simv_debug) - cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] + cd $(sim_dir) && $(exec_simv_debug) +permissive +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] $(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) - cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] + cd $(sim_dir) && $(exec_simv_debug) +permissive +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] $(output_dir)/%.saif: $(output_dir)/% $(simv_debug) - cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1 + cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +permissive +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +permissive-off $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1 run: run-asm-tests run-bmark-tests run-debug: run-asm-tests-debug run-bmark-tests-debug