Merge pull request #1105 from freechipsproject/axi4-xbar
axi4: add an Xbar
This commit is contained in:
Wesley W. Terpstra
GitHub
commit
8b79f0394e
@ -40,9 +40,9 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
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val qs = Seq.tabulate(endId) { i =>
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val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0)
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if (depth > 0) {
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Module(new Queue(out.r.bits, beats)).io
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Module(new Queue(out.r.bits.cloneType, beats)).io
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} else {
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Wire(new QueueIO(out.r.bits, beats))
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Wire(new QueueIO(out.r.bits.cloneType, beats))
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}
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}
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83
src/main/scala/amba/axi4/Delayer.scala
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83
src/main/scala/amba/axi4/Delayer.scala
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@ -0,0 +1,83 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink.LFSRNoiseMaker
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// q is the probability to delay a request
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class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4AdapterNode()
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require (0.0 <= q && q < 1)
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lazy val module = new LazyModuleImp(this) {
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def feed[T <: Data](sink: IrrevocableIO[T], source: IrrevocableIO[T], noise: T) {
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// irrevocable requires that we not lower valid
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val hold = RegInit(Bool(false))
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when (sink.valid) { hold := Bool(true) }
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when (sink.fire()) { hold := Bool(false) }
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val allow = hold || UInt((q * 65535.0).toInt) <= LFSRNoiseMaker(16, source.valid)
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sink.valid := source.valid && allow
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source.ready := sink.ready && allow
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sink.bits := source.bits
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when (!sink.valid) { sink.bits := noise }
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}
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def anoise[T <: AXI4BundleA](bits: T) {
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bits.id := LFSRNoiseMaker(bits.params.idBits)
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bits.addr := LFSRNoiseMaker(bits.params.addrBits)
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bits.len := LFSRNoiseMaker(bits.params.lenBits)
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bits.size := LFSRNoiseMaker(bits.params.sizeBits)
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bits.burst := LFSRNoiseMaker(bits.params.burstBits)
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bits.lock := LFSRNoiseMaker(bits.params.lockBits)
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bits.cache := LFSRNoiseMaker(bits.params.cacheBits)
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bits.prot := LFSRNoiseMaker(bits.params.protBits)
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bits.qos := LFSRNoiseMaker(bits.params.qosBits)
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if (bits.params.userBits > 0)
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bits.user.get := LFSRNoiseMaker(bits.params.userBits)
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}
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(node.in zip node.out) foreach { case ((in, _), (out, _)) =>
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val arnoise = Wire(in.ar.bits)
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val awnoise = Wire(in.aw.bits)
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val wnoise = Wire(in.w .bits)
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val rnoise = Wire(in.r .bits)
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val bnoise = Wire(in.b .bits)
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anoise(arnoise)
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anoise(awnoise)
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wnoise.data := LFSRNoiseMaker(wnoise.params.dataBits)
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wnoise.strb := LFSRNoiseMaker(wnoise.params.dataBits/8)
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wnoise.last := LFSRNoiseMaker(1)(0)
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rnoise.id := LFSRNoiseMaker(rnoise.params.idBits)
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rnoise.data := LFSRNoiseMaker(rnoise.params.dataBits)
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rnoise.resp := LFSRNoiseMaker(rnoise.params.respBits)
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rnoise.last := LFSRNoiseMaker(1)(0)
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if (rnoise.params.userBits > 0)
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rnoise.user.get := LFSRNoiseMaker(rnoise.params.userBits)
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bnoise.id := LFSRNoiseMaker(bnoise.params.idBits)
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bnoise.resp := LFSRNoiseMaker(bnoise.params.respBits)
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if (bnoise.params.userBits > 0)
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bnoise.user.get := LFSRNoiseMaker(bnoise.params.userBits)
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feed(out.ar, in.ar, arnoise)
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feed(out.aw, in.aw, awnoise)
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feed(out.w, in.w, wnoise)
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feed(in.b, out.b, bnoise)
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feed(in.r, out.r, rnoise)
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}
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}
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}
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object AXI4Delayer
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{
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def apply(q: Double)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Delayer(q)).node
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}
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62
src/main/scala/amba/axi4/Filter.scala
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62
src/main/scala/amba/axi4/Filter.scala
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@ -0,0 +1,62 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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class AXI4Filter(
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Sfilter: AXI4SlaveParameters => Option[AXI4SlaveParameters] = AXI4Filter.Sidentity,
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Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters] = AXI4Filter.Midentity
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)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4AdapterNode(
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slaveFn = { sp => sp.copy(slaves = sp.slaves.flatMap { s =>
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val out = Sfilter(s)
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out.foreach { o => // Confirm the filter only REMOVES capability
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o.address.foreach { a => require (s.address.map(_.contains(a)).reduce(_||_)) }
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require (o.regionType <= s.regionType)
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// we allow executable to be changed both ways
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require (s.supportsWrite.contains(o.supportsWrite))
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require (s.supportsRead .contains(o.supportsRead))
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require (!o.interleavedId.isDefined || s.interleavedId == o.interleavedId)
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}
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out
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})},
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masterFn = { mp => mp.copy(masters = mp.masters.flatMap { m =>
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val out = Mfilter(m)
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out.foreach { o => require (m.id.contains(o.id)) }
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out
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})})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out <> in
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}
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}
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}
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object AXI4Filter
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{
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def Midentity: AXI4MasterParameters => Option[AXI4MasterParameters] = { m => Some(m) }
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def Sidentity: AXI4SlaveParameters => Option[AXI4SlaveParameters] = { s => Some(s) }
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def Smask(select: AddressSet): AXI4SlaveParameters => Option[AXI4SlaveParameters] = { s =>
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val filtered = s.address.map(_.intersect(select)).flatten
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val alignment = select.alignment /* alignment 0 means 'select' selected everything */
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val maxTransfer = 1 << 30
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val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt
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val cap = TransferSizes(1, capTransfer)
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if (filtered.isEmpty) { None } else {
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Some(s.copy(
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address = filtered,
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supportsWrite = s.supportsWrite.intersect(cap),
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supportsRead = s.supportsRead .intersect(cap)))
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}
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}
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def apply(
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Sfilter: AXI4SlaveParameters => Option[AXI4SlaveParameters] = AXI4Filter.Sidentity,
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Mfilter: AXI4MasterParameters => Option[AXI4MasterParameters] = AXI4Filter.Midentity
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)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Filter(Sfilter, Mfilter)).node
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}
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@ -21,9 +21,16 @@ object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortPara
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case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters])(implicit valName: ValName) extends SourceNode(AXI4Imp)(portParams)
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case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters])(implicit valName: ValName) extends SinkNode(AXI4Imp)(portParams)
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case class AXI4NexusNode(
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masterFn: Seq[AXI4MasterPortParameters] => AXI4MasterPortParameters,
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slaveFn: Seq[AXI4SlavePortParameters] => AXI4SlavePortParameters,
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numMasterPorts: Range.Inclusive = 1 to 999,
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numSlavePorts: Range.Inclusive = 1 to 999)(
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implicit valName: ValName)
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extends NexusNode(AXI4Imp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
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case class AXI4AdapterNode(
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masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters,
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slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters,
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masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters = { m => m },
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slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters = { s => s },
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numPorts: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts)
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@ -90,3 +90,14 @@ class AXI4RAM(
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in.r.bits.last := Bool(true)
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}
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}
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object AXI4RAM
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{
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def apply(
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address: AddressSet,
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executable: Boolean = true,
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beatBytes: Int = 4,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)
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(implicit p: Parameters) = LazyModule(new AXI4RAM(address, executable, beatBytes, devName, errors)).node
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}
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315
src/main/scala/amba/axi4/Xbar.scala
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315
src/main/scala/amba/axi4/Xbar.scala
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@ -0,0 +1,315 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.unittest._
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import freechips.rocketchip.tilelink._
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class AXI4Xbar(
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arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
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maxFlightPerId: Int = 7,
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awQueueDepth: Int = 2)(implicit p: Parameters) extends LazyModule
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{
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require (maxFlightPerId >= 1)
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require (awQueueDepth >= 1)
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val node = AXI4NexusNode(
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numMasterPorts = 1 to 999,
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numSlavePorts = 1 to 999,
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masterFn = { seq =>
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seq(0).copy(
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userBits = seq.map(_.userBits).max,
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masters = (AXI4Xbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
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port.masters map { master => master.copy(id = master.id.shift(range.start)) }
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}
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)
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},
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slaveFn = { seq =>
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seq(0).copy(
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minLatency = seq.map(_.minLatency).min,
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slaves = seq.flatMap { port =>
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require (port.beatBytes == seq(0).beatBytes,
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s"Xbar data widths don't match: ${port.slaves.map(_.name)} has ${port.beatBytes}B vs ${seq(0).slaves.map(_.name)} has ${seq(0).beatBytes}B")
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port.slaves
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}
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)
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})
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lazy val module = new LazyModuleImp(this) {
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val (io_in, edgesIn) = node.in.unzip
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val (io_out, edgesOut) = node.out.unzip
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// Grab the port ID mapping
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val inputIdRanges = AXI4Xbar.mapInputIds(edgesIn.map(_.master))
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// Find a good mask for address decoding
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val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
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val routingMask = AddressDecoder(port_addrs)
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val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
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val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
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// To route W we need to record where the AWs went
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val awIn = Seq.fill(io_in .size) { Module(new Queue(UInt(width = io_out.size), awQueueDepth, flow = true)) }
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val awOut = Seq.fill(io_out.size) { Module(new Queue(UInt(width = io_in .size), awQueueDepth, flow = true)) }
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val requestARIO = Vec(io_in.map { i => Vec(outputPorts.map { o => o(i.ar.bits.addr) }) })
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val requestAWIO = Vec(io_in.map { i => Vec(outputPorts.map { o => o(i.aw.bits.addr) }) })
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val requestROI = Vec(io_out.map { o => Vec(inputIdRanges.map { i => i.contains(o.r.bits.id) }) })
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val requestBOI = Vec(io_out.map { o => Vec(inputIdRanges.map { i => i.contains(o.b.bits.id) }) })
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// W follows the path dictated by the AW Q
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for (i <- 0 until io_in.size) { awIn(i).io.enq.bits := requestAWIO(i).asUInt }
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val requestWIO = Vec(awIn.map { q => if (io_out.size > 1) Vec(q.io.deq.bits.toBools) else Vec.fill(1){Bool(true)} })
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// We need an intermediate size of bundle with the widest possible identifiers
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val wide_bundle = AXI4BundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
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// Transform input bundles
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val in = Wire(Vec(io_in.size, AXI4Bundle(wide_bundle)))
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for (i <- 0 until in.size) {
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in(i) <> io_in(i)
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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// Manipulate the AXI IDs to differentiate masters
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val r = inputIdRanges(i)
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in(i).aw.bits.id := io_in(i).aw.bits.id | UInt(r.start)
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in(i).ar.bits.id := io_in(i).ar.bits.id | UInt(r.start)
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io_in(i).r.bits.id := trim(in(i).r.bits.id, r.size)
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io_in(i).b.bits.id := trim(in(i).b.bits.id, r.size)
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if (io_out.size > 1) {
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// Block A[RW] if we switch ports, to ensure responses stay ordered (also: beware the dining philosophers)
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val endId = edgesIn(i).master.endId
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val arFIFOMap = Wire(init = Vec.fill(endId) { Bool(true) })
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val awFIFOMap = Wire(init = Vec.fill(endId) { Bool(true) })
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val arSel = UIntToOH(io_in(i).ar.bits.id, endId)
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val awSel = UIntToOH(io_in(i).aw.bits.id, endId)
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val rSel = UIntToOH(io_in(i).r .bits.id, endId)
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val bSel = UIntToOH(io_in(i).b .bits.id, endId)
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val arTag = OHToUInt(requestARIO(i).asUInt, io_out.size)
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val awTag = OHToUInt(requestAWIO(i).asUInt, io_out.size)
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for (master <- edgesIn(i).master.masters) {
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def idTracker(port: UInt, req_fire: Bool, resp_fire: Bool) = {
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if (master.maxFlight == Some(0)) {
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Bool(true)
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} else {
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val legalFlight = master.maxFlight.getOrElse(maxFlightPerId+1)
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val flight = legalFlight min maxFlightPerId
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val canOverflow = legalFlight > flight
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val count = RegInit(UInt(0, width = log2Ceil(flight+1)))
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val last = Reg(UInt(width = log2Ceil(io_out.size)))
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count := count + req_fire.asUInt - resp_fire.asUInt
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assert (!resp_fire || count =/= UInt(0))
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assert (!req_fire || count =/= UInt(flight))
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when (req_fire) { last := port }
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// No need to track where it went if we cap it at 1 request
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val portMatch = if (flight == 1) { Bool(true) } else { last === port }
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(count === UInt(0) || portMatch) && (Bool(!canOverflow) || count =/= UInt(flight))
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}
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}
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for (id <- master.id.start until master.id.end) {
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arFIFOMap(id) := idTracker(
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arTag,
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arSel(id) && io_in(i).ar.fire(),
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rSel(id) && io_in(i).r.fire() && io_in(i).r.bits.last)
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awFIFOMap(id) := idTracker(
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awTag,
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awSel(id) && io_in(i).aw.fire(),
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bSel(id) && io_in(i).b.fire())
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}
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}
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val allowAR = arFIFOMap(io_in(i).ar.bits.id)
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in(i).ar.valid := io_in(i).ar.valid && allowAR
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io_in(i).ar.ready := in(i).ar.ready && allowAR
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// Keep in mind that slaves may do this: awready := wvalid, wready := awvalid
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// To not cause a loop, we cannot have: wvalid := awready
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// Block AW if we cannot record the W destination
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val allowAW = awFIFOMap(io_in(i).aw.bits.id)
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val latched = RegInit(Bool(false)) // cut awIn(i).enq.valid from awready
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in(i).aw.valid := io_in(i).aw.valid && (latched || awIn(i).io.enq.ready) && allowAW
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io_in(i).aw.ready := in(i).aw.ready && (latched || awIn(i).io.enq.ready) && allowAW
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awIn(i).io.enq.valid := io_in(i).aw.valid && !latched
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when (awIn(i).io.enq.fire()) { latched := Bool(true) }
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when (in(i).aw.fire()) { latched := Bool(false) }
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// Block W if we do not have an AW destination
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in(i).w.valid := io_in(i).w.valid && awIn(i).io.deq.valid // depends on awvalid (but not awready)
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io_in(i).w.ready := in(i).w.ready && awIn(i).io.deq.valid
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awIn(i).io.deq.ready := io_in(i).w.valid && io_in(i).w.bits.last && in(i).w.ready
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}
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}
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// Transform output bundles
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val out = Wire(Vec(io_out.size, AXI4Bundle(wide_bundle)))
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for (i <- 0 until out.size) {
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io_out(i) <> out(i)
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if (io_in.size > 1) {
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// Block AW if we cannot record the W source
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val latched = RegInit(Bool(false)) // cut awOut(i).enq.valid from awready
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io_out(i).aw.valid := out(i).aw.valid && (latched || awOut(i).io.enq.ready)
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out(i).aw.ready := io_out(i).aw.ready && (latched || awOut(i).io.enq.ready)
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awOut(i).io.enq.valid := out(i).aw.valid && !latched
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when (awOut(i).io.enq.fire()) { latched := Bool(true) }
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when (out(i).aw.fire()) { latched := Bool(false) }
|
||||
|
||||
// Block W if we do not have an AW source
|
||||
io_out(i).w.valid := out(i).w.valid && awOut(i).io.deq.valid // depends on awvalid (but not awready)
|
||||
out(i).w.ready := io_out(i).w.ready && awOut(i).io.deq.valid
|
||||
awOut(i).io.deq.ready := out(i).w.valid && out(i).w.bits.last && io_out(i).w.ready
|
||||
}
|
||||
}
|
||||
|
||||
// Fanout the input sources to the output sinks
|
||||
def transpose[T](x: Seq[Seq[T]]) = Seq.tabulate(x(0).size) { i => Seq.tabulate(x.size) { j => x(j)(i) } }
|
||||
val portsAROI = transpose((in zip requestARIO) map { case (i, r) => AXI4Xbar.fanout(i.ar, r) })
|
||||
val portsAWOI = transpose((in zip requestAWIO) map { case (i, r) => AXI4Xbar.fanout(i.aw, r) })
|
||||
val portsWOI = transpose((in zip requestWIO) map { case (i, r) => AXI4Xbar.fanout(i.w, r) })
|
||||
val portsRIO = transpose((out zip requestROI) map { case (o, r) => AXI4Xbar.fanout(o.r, r) })
|
||||
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => AXI4Xbar.fanout(o.b, r) })
|
||||
|
||||
// Arbitrate amongst the sources
|
||||
for (o <- 0 until out.size) {
|
||||
awOut(o).io.enq.bits := // Record who won AW arbitration to select W
|
||||
AXI4Arbiter.returnWinner(arbitrationPolicy)(out(o).aw, portsAWOI(o):_*).asUInt
|
||||
AXI4Arbiter(arbitrationPolicy)(out(o).ar, portsAROI(o):_*)
|
||||
// W arbitration is informed by the Q, not policy
|
||||
out(o).w.valid := Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.valid))
|
||||
out(o).w.bits := Mux1H(awOut(o).io.deq.bits, portsWOI(o).map(_.bits))
|
||||
portsWOI(o).zipWithIndex.map { case (p, i) =>
|
||||
if (in.size > 1) {
|
||||
p.ready := out(o).w.ready && awOut(o).io.deq.bits(i)
|
||||
} else {
|
||||
p.ready := out(o).w.ready
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i <- 0 until in.size) {
|
||||
AXI4Arbiter(arbitrationPolicy)(in(i).r, portsRIO(i):_*)
|
||||
AXI4Arbiter(arbitrationPolicy)(in(i).b, portsBIO(i):_*)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
object AXI4Xbar
|
||||
{
|
||||
def apply(
|
||||
arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
|
||||
maxFlightPerId: Int = 7,
|
||||
awQueueDepth: Int = 2)(implicit p: Parameters) = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth)).node
|
||||
|
||||
def mapInputIds(ports: Seq[AXI4MasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)).map(_.get)
|
||||
|
||||
// Replicate an input port to each output port
|
||||
def fanout[T <: AXI4BundleBase](input: IrrevocableIO[T], select: Seq[Bool]) = {
|
||||
val filtered = Wire(Vec(select.size, input))
|
||||
for (i <- 0 until select.size) {
|
||||
filtered(i).bits := input.bits
|
||||
filtered(i).valid := input.valid && select(i)
|
||||
}
|
||||
input.ready := Mux1H(select, filtered.map(_.ready))
|
||||
filtered
|
||||
}
|
||||
}
|
||||
|
||||
object AXI4Arbiter
|
||||
{
|
||||
def apply[T <: Data](policy: TLArbiter.Policy)(sink: IrrevocableIO[T], sources: IrrevocableIO[T]*) {
|
||||
if (sources.isEmpty) {
|
||||
sink.valid := Bool(false)
|
||||
} else {
|
||||
returnWinner(policy)(sink, sources:_*)
|
||||
}
|
||||
}
|
||||
def returnWinner[T <: Data](policy: TLArbiter.Policy)(sink: IrrevocableIO[T], sources: IrrevocableIO[T]*) = {
|
||||
require (!sources.isEmpty)
|
||||
|
||||
// The arbiter is irrevocable; when !idle, repeat last request
|
||||
val idle = RegInit(Bool(true))
|
||||
|
||||
// Who wants access to the sink?
|
||||
val valids = sources.map(_.valid)
|
||||
val anyValid = valids.reduce(_ || _)
|
||||
// Arbitrate amongst the requests
|
||||
val readys = Vec(policy(valids.size, Cat(valids.reverse), idle).toBools)
|
||||
// Which request wins arbitration?
|
||||
val winner = Vec((readys zip valids) map { case (r,v) => r&&v })
|
||||
|
||||
// Confirm the policy works properly
|
||||
require (readys.size == valids.size)
|
||||
// Never two winners
|
||||
val prefixOR = winner.scanLeft(Bool(false))(_||_).init
|
||||
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
|
||||
// If there was any request, there is a winner
|
||||
assert (!anyValid || winner.reduce(_||_))
|
||||
|
||||
// The one-hot source granted access in the previous cycle
|
||||
val state = RegInit(Vec.fill(sources.size)(Bool(false)))
|
||||
val muxState = Mux(idle, winner, state)
|
||||
state := muxState
|
||||
|
||||
// Determine when we go idle
|
||||
when (anyValid) { idle := Bool(false) }
|
||||
when (sink.fire()) { idle := Bool(true) }
|
||||
|
||||
if (sources.size > 1) {
|
||||
val allowed = Mux(idle, readys, state)
|
||||
(sources zip allowed) foreach { case (s, r) =>
|
||||
s.ready := sink.ready && r
|
||||
}
|
||||
} else {
|
||||
sources(0).ready := sink.ready
|
||||
}
|
||||
|
||||
sink.valid := Mux(idle, anyValid, Mux1H(state, valids))
|
||||
sink.bits := Mux1H(muxState, sources.map(_.bits))
|
||||
muxState
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4XbarFuzzTest(name: String, txns: Int, nMasters: Int, nSlaves: Int)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val xbar = AXI4Xbar()
|
||||
val slaveSize = 0x1000
|
||||
val masterBandSize = slaveSize >> log2Ceil(nMasters)
|
||||
def filter(i: Int) = TLFilter.Mmask(AddressSet(i * masterBandSize, ~BigInt(slaveSize - masterBandSize)))
|
||||
|
||||
val slaves = Seq.tabulate(nSlaves) { i => LazyModule(new AXI4RAM(AddressSet(slaveSize * i, slaveSize-1))) }
|
||||
slaves.foreach { s => (s.node
|
||||
:= AXI4Fragmenter()
|
||||
:= AXI4Buffer(BufferParams.flow)
|
||||
:= AXI4Buffer(BufferParams.flow)
|
||||
:= AXI4Delayer(0.25)
|
||||
:= xbar) }
|
||||
|
||||
val masters = Seq.fill(nMasters) { LazyModule(new TLFuzzer(txns, 4, nOrdered = Some(1))) }
|
||||
masters.zipWithIndex.foreach { case (m, i) => (xbar
|
||||
:= AXI4Delayer(0.25)
|
||||
:= AXI4Deinterleaver(4096)
|
||||
:= TLToAXI4()
|
||||
:= TLFilter(filter(i))
|
||||
:= TLRAMModel(s"${name} Master $i")
|
||||
:= m.node) }
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := masters.map(_.module.io.finished).reduce(_ || _)
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4XbarTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
|
||||
val dut21 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT21", txns, 2, 1)).module)
|
||||
val dut12 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT12", txns, 1, 2)).module)
|
||||
val dut22 = Module(LazyModule(new AXI4XbarFuzzTest("Xbar DUT22", txns, 2, 2)).module)
|
||||
io.finished := Seq(dut21, dut12, dut22).map(_.io.finished).reduce(_ || _)
|
||||
}
|
||||
@ -99,7 +99,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
|
||||
|
||||
val (tl_out_c, release_queue_empty) =
|
||||
if (cacheParams.acquireBeforeRelease) {
|
||||
val q = Module(new Queue(tl_out.c.bits, cacheDataBeats, flow = true))
|
||||
val q = Module(new Queue(tl_out.c.bits.cloneType, cacheDataBeats, flow = true))
|
||||
tl_out.c <> q.io.deq
|
||||
(q.io.enq, q.io.count === 0)
|
||||
} else {
|
||||
|
||||
@ -42,7 +42,7 @@ class TLFilter(
|
||||
require (m.supportsPutFull.contains(o.supportsPutFull))
|
||||
require (m.supportsPutPartial.contains(o.supportsPutPartial))
|
||||
require (m.supportsHint.contains(o.supportsHint))
|
||||
require (m.fifoId == o.fifoId) // could relax this, but hard to validate
|
||||
require (!o.fifoId.isDefined || m.fifoId == o.fifoId)
|
||||
}
|
||||
out
|
||||
})})
|
||||
|
||||
@ -333,6 +333,9 @@ class TLRAMModel(log: String = "", ignoreErrorData: Boolean = false)(implicit p:
|
||||
|
||||
object TLRAMModel
|
||||
{
|
||||
def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters) =
|
||||
LazyModule(new TLRAMModel(log, ignoreErrorData)).node
|
||||
|
||||
case class MonitorParameters(addressBits: Int, sizeBits: Int)
|
||||
|
||||
class ByteMonitor(params: MonitorParameters) extends GenericParameterizedBundle(params) {
|
||||
|
||||
@ -31,6 +31,7 @@ class WithAMBAUnitTests extends Config((site, here, up) => {
|
||||
Module(new AXI4LiteFuzzRAMTest(txns=6*txns, timeout=timeout)),
|
||||
Module(new AXI4FullFuzzRAMTest(txns=3*txns, timeout=timeout)),
|
||||
Module(new AXI4BridgeTest( txns=3*txns, timeout=timeout)),
|
||||
Module(new AXI4XbarTest( txns=1*txns, timeout=timeout)),
|
||||
Module(new AXI4RAMAsyncCrossingTest(txns=3*txns, timeout=timeout))) }
|
||||
})
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user