riscv/rocket-chip
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add external memory request interface for vec unit

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This commit is contained in:
Andrew Waterman
2012-02-08 22:30:45 -08:00
parent 9285a52f25
commit 8b6b0f5367
4 changed files with 41 additions and 25 deletions
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2
rocket/src/main/scala/consts.scala
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@ -171,7 +171,7 @@ object Constants
// rocketNBDCacheDM parameters
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 6;
val CPU_TAG_BITS = 9;
val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
val OFFSET_BITS = 6; // log2(cache line size in bytes)
val NMSHR = 2; // number of primary misses