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axi4: conversion from TL does not need beatBytes (#1051)

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We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
This commit is contained in:
Wesley W. Terpstra
2017-10-12 16:41:54 -07:00
committed by GitHub
parent 21b5367259
commit 8b58327fa4
4 changed files with 15 additions and 15 deletions
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4
src/main/scala/coreplex/Ports.scala
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@ -49,7 +49,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
beatBytes = params.beatBytes)
})
val converter = LazyModule(new TLToAXI4(params.beatBytes))
val converter = LazyModule(new TLToAXI4())
val trim = LazyModule(new AXI4IdIndexer(params.idBits))
val yank = LazyModule(new AXI4UserYanker)
val buffer = LazyModule(new AXI4Buffer)
@ -102,7 +102,7 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
AXI4UserYanker()(
AXI4Deinterleaver(sbus.blockBytes)(
AXI4IdIndexer(params.idBits)(
TLToAXI4(params.beatBytes)(
TLToAXI4()(
sbus.toFixedWidthPorts)))))
}