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axi4: conversion from TL does not need beatBytes (#1051)

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We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
This commit is contained in:
Wesley W. Terpstra
2017-10-12 16:41:54 -07:00
committed by GitHub
parent 21b5367259
commit 8b58327fa4
4 changed files with 15 additions and 15 deletions
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2
src/main/scala/amba/axi4/AsyncCrossing.scala
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@ -91,7 +91,7 @@ class AXI4RAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule
val model = LazyModule(new TLRAMModel("AsyncCrossing"))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
val fuzz = LazyModule(new TLFuzzer(txns))
val toaxi = LazyModule(new TLToAXI4(beatBytes = 4))
val toaxi = LazyModule(new TLToAXI4)
val cross = LazyModule(new AXI4AsyncCrossing)
model.node := fuzz.node

10
src/main/scala/amba/axi4/Test.scala
View File

@ -27,8 +27,8 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(4, true )(TLFragmenter(4, 16)(xbar.node))))
gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(4, false)(TLFragmenter(4, 16)(xbar.node))))
ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(true )(TLFragmenter(4, 16)(xbar.node))))
gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(false)(TLFragmenter(4, 16)(xbar.node))))
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
@ -50,8 +50,8 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,false)(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,true )(xbar.node)))
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(false)(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(true )(xbar.node)))
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
@ -77,7 +77,7 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with
node :=
AXI4UserYanker()(
AXI4Deinterleaver(64)(
TLToAXI4(4)(
TLToAXI4()(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(