riscv/rocket-chip
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Add Matthew Naylor's trace generator and AXE scripts

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This commit is contained in:
Howard Mao
2016-02-22 10:04:38 -08:00
parent 8c02cb09ca
commit 8a877fa620
7 changed files with 191 additions and 2 deletions
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10
src/main/scala/TestConfigs.scala
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@@ -114,6 +114,15 @@ class WithUnitTest extends Config(
(id: Int, p: Parameters) => Module(new UnitTestSuite()(p))
})
class WithTraceGen extends Config(
(pname, site, here) => pname match {
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new GroundTestTraceGenerator(id)(p))
case NGenerators => site(NTiles)
case MaxGenerateRequests => 128
case AddressBag => List(0x8, 0x10, 0x108, 0x100008)
})
class GroundTestConfig extends Config(new WithGroundTest ++ new DefaultConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
@@ -128,6 +137,7 @@ class DmaTestConfig extends Config(new WithDmaTest ++ new WithL2Cache ++ new Gro
class DmaStreamTestConfig extends Config(new WithDmaStreamTest ++ new WithStreamLoopback ++ new WithL2Cache ++ new GroundTestConfig)
class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig)
class FancyMemtestConfig extends Config(
new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++