riscv/rocket-chip
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fix D$ writeback bug

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I swear I did this last week... perhaps I am finally losing it!
This commit is contained in:
Andrew Waterman 2012-11-25 19:46:48 -08:00
parent de2f28193a
commit 8a6ff5f9aa
2 changed files with 40 additions and 33 deletions
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66
rocket/src/main/scala/nbdcache.scala
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@ -414,41 +414,47 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
} }
val valid = Reg(resetVal = Bool(false)) val valid = Reg(resetVal = Bool(false))
val is_probe = Reg() { Bool() } val is_probe = Reg{Bool()}
val data_req_fired = Reg(resetVal = Bool(false)) val r1_data_req_fired = Reg(resetVal = Bool(false))
val r_data_req_fired = Reg(data_req_fired, resetVal = Bool(false)) val r2_data_req_fired = Reg(resetVal = Bool(false))
val cmd_sent = Reg() { Bool() } val cmd_sent = Reg{Bool()}
val cnt = Reg() { UFix(width = log2Up(REFILL_CYCLES+1)) } val cnt = Reg{UFix(width = log2Up(REFILL_CYCLES+1))}
val req = Reg() { new WritebackReq() } val req = Reg{new WritebackReq}
val dout_rdy = Mux(is_probe, io.probe_rep_data.ready, io.mem_req_data.ready) when (valid) {
data_req_fired := Bool(false) r1_data_req_fired := false
when (valid && io.mem_req.ready) { r2_data_req_fired := r1_data_req_fired
cmd_sent := Bool(true)
}
when (io.data_req.fire()) { when (io.data_req.fire()) {
data_req_fired := Bool(true) r1_data_req_fired := true
cnt := cnt + UFix(1) cnt := cnt + 1
} }
when (data_req_fired && !dout_rdy) {
data_req_fired := Bool(false) when (r2_data_req_fired && !Mux(is_probe, io.probe_rep_data.ready, io.mem_req_data.ready)) {
cnt := cnt - UFix(1) r1_data_req_fired := false
r2_data_req_fired := false
cnt := cnt - Mux[UFix](r1_data_req_fired, 2, 1)
} }
.elsewhen (cmd_sent && (cnt === UFix(REFILL_CYCLES))) {
valid := Bool(false) when (!r1_data_req_fired && !r2_data_req_fired && cmd_sent && cnt === REFILL_CYCLES) {
valid := false
} }
when (io.probe.valid && io.probe.ready) {
valid := Bool(true) when (valid && io.mem_req.ready) {
is_probe := Bool(true) cmd_sent := true
cmd_sent := Bool(true) }
cnt := UFix(0) }
when (io.probe.fire()) {
valid := true
is_probe := true
cmd_sent := true
cnt := 0
req := io.probe.bits req := io.probe.bits
} }
when (io.req.valid && io.req.ready) { when (io.req.fire()) {
valid := Bool(true) valid := true
is_probe := Bool(false) is_probe := false
cmd_sent := Bool(false) cmd_sent := false
cnt := UFix(0) cnt := 0
req := io.req.bits req := io.req.bits
} }
@ -463,9 +469,9 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback() io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback()
io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
io.mem_req.bits.tile_xact_id := req.tile_xact_id io.mem_req.bits.tile_xact_id := req.tile_xact_id
io.mem_req_data.valid := r_data_req_fired && !is_probe io.mem_req_data.valid := r2_data_req_fired && !is_probe
io.mem_req_data.bits.data := io.data_resp io.mem_req_data.bits.data := io.data_resp
io.probe_rep_data.valid := r_data_req_fired && is_probe io.probe_rep_data.valid := r2_data_req_fired && is_probe
io.probe_rep_data.bits.data := io.data_resp io.probe_rep_data.bits.data := io.data_resp
io.meta_read.valid := fire && io.data_req.ready io.meta_read.valid := fire && io.data_req.ready

1
rocket/src/main/scala/util.scala
View File

@ -7,6 +7,7 @@ object Util
implicit def intToUFix(x: Int): UFix = UFix(x) implicit def intToUFix(x: Int): UFix = UFix(x)
implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false
implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def wcToUFix(c: WideCounter): UFix = c.value implicit def wcToUFix(c: WideCounter): UFix = c.value
} }