move memory width adapter from coreplex to periphery

src/main/scala/coreplex/BaseCoreplex.scala

@@ -31,7 +31,7 @@ trait HasCoreplexParameters {
   lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
   lazy val lsb = p(BankIdLSB)
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
-  lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
+  lazy val outerParams = p.alterPartial({ case TLId => "L2toMC" })
   lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
   lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
 }
@@ -50,7 +50,7 @@ abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends L
 
 abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
   val master = new Bundle {
-    val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
+    val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerParams))
     val mmio = new ClientUncachedTileLinkIO()(outerMMIOParams)
   }
   val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
@@ -112,14 +112,12 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
     l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
 
     // Create a converter between TileLinkIO and MemIO for each channel
-    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outermostParams))
+    val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerParams))
 
-    val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
     val backendBuffering = TileLinkDepths(0,0,0,0,0)
     for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
       val enqueued = TileLinkEnqueuer(bank.outerTL, backendBuffering)
-      val unwrapped = TileLinkIOUnwrapper(enqueued)
+      icPort <> TileLinkIOUnwrapper(enqueued)
-      TileLinkWidthAdapter(icPort, unwrapped)
     }
 
     io.master.mem <> mem_ic.io.out

src/main/scala/coreplex/Configs.scala

@@ -132,15 +132,11 @@ class BaseCoreplexConfig extends Config (
           nManagers = 1,
           nCachingClients = site(NBanksPerMemoryChannel),
           nCachelessClients = 0,
-          maxClientXacts = 1,
+          maxClientXacts = site(NAcquireTransactors) + 2,
-          maxClientsPerPort = site(NAcquireTransactors) + 2,
+          maxClientsPerPort = site(NBanksPerMemoryChannel),
           maxManagerXacts = 1,
           dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes)*8)
-      case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
-        maxClientXacts = site(NAcquireTransactors) + 2,
-        maxClientsPerPort = site(NBanksPerMemoryChannel),
-        dataBeats = site(MIFDataBeats))
       case TLKey("L2toMMIO") => {
         TileLinkParameters(
           coherencePolicy = new MICoherence(
@@ -154,7 +150,6 @@ class BaseCoreplexConfig extends Config (
           dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes) * 8)
       }
-      case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
 
       case BootROMFile => "./bootrom/bootrom.img"
       case NTiles => 1

src/main/scala/rocketchip/Configs.scala

@@ -39,6 +39,10 @@ class BasePlatformConfig extends Config(
             addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
             idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
         }
+        case TLKey("Outermost") =>
+          site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
+        case TLKey("MMIO_Outermost") =>
+          site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
         case BuildCoreplex =>
           (c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module
         case NExtTopInterrupts => 2

src/main/scala/rocketchip/Periphery.scala

@@ -82,6 +82,7 @@ trait HasPeripheryParameters {
   lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
   lazy val nMemTLChannels  = if (tMemChannels == BusType.TL)  nMemChannels else 0
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
+  lazy val outerParams = p.alterPartial({ case TLId => "L2toMC" })
   lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
   lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
   lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
@@ -171,8 +172,10 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
   val io: PeripheryMasterMemBundle
   val coreplexIO: BaseCoreplexBundle
 
+  val edgeMem = coreplexIO.master.mem.map(TileLinkWidthAdapter(_, outermostParams))
+
   // Abuse the fact that zip takes the shorter of the two lists
-  ((io.mem_axi zip coreplexIO.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
+  ((io.mem_axi zip edgeMem) zipWithIndex) foreach { case ((axi, mem), idx) =>
     val axi_sync = PeripheryUtils.convertTLtoAXI(mem)
     axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF
     axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF
@@ -182,11 +185,11 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
     )
   }
 
-  (io.mem_ahb zip coreplexIO.master.mem) foreach { case (ahb, mem) =>
+  (io.mem_ahb zip edgeMem) foreach { case (ahb, mem) =>
     ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)
   }
 
-  (io.mem_tl zip coreplexIO.master.mem) foreach { case (tl, mem) =>
+  (io.mem_tl zip edgeMem) foreach { case (tl, mem) =>
     tl <> TileLinkEnqueuer(mem, 2)
   }
 }