riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

move memory width adapter from coreplex to periphery

Browse Source
This commit is contained in:
Howard Mao authored and Henry Cook committed 2016-09-27 12:48:01 -07:00
1 parent e36441a046
commit 8a55521b01
4 files changed
+16 -16
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/rocketchip/Configs.scala
+4
View File
@@ -39,6 +39,10 @@ class BasePlatformConfig extends Config(
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
}
case TLKey("Outermost") =>
site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case TLKey("MMIO_Outermost") =>
site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case BuildCoreplex =>
(c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module
case NExtTopInterrupts => 2