riscv/rocket-chip
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move memory width adapter from coreplex to periphery

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This commit is contained in:
Howard Mao
2016-09-27 11:33:20 -07:00
committed by Henry Cook
parent e36441a046
commit 8a55521b01
4 changed files with 16 additions and 16 deletions
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4
src/main/scala/rocketchip/Configs.scala
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@ -39,6 +39,10 @@ class BasePlatformConfig extends Config(
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
}
case TLKey("Outermost") =>
site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case TLKey("MMIO_Outermost") =>
site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case BuildCoreplex =>
(c: CoreplexConfig, p: Parameters) => uncore.tilelink2.LazyModule(new DefaultCoreplex(c)(p)).module
case NExtTopInterrupts => 2