riscv/rocket-chip
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move memory width adapter from coreplex to periphery

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This commit is contained in:
Howard Mao
2016-09-27 11:33:20 -07:00
committed by Henry Cook
parent e36441a046
commit 8a55521b01
4 changed files with 16 additions and 16 deletions
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9
src/main/scala/coreplex/Configs.scala
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@ -132,15 +132,11 @@ class BaseCoreplexConfig extends Config (
nManagers = 1,
nCachingClients = site(NBanksPerMemoryChannel),
nCachelessClients = 0,
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
maxManagerXacts = 1,
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
TileLinkParameters(
coherencePolicy = new MICoherence(
@ -154,7 +150,6 @@ class BaseCoreplexConfig extends Config (
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes) * 8)
}
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case BootROMFile => "./bootrom/bootrom.img"
case NTiles => 1