riscv/rocket-chip
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move memory width adapter from coreplex to periphery

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This commit is contained in:
Howard Mao
2016-09-27 11:33:20 -07:00
committed by Henry Cook
parent e36441a046
commit 8a55521b01
4 changed files with 16 additions and 16 deletions
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10
src/main/scala/coreplex/BaseCoreplex.scala
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@ -31,7 +31,7 @@ trait HasCoreplexParameters {
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val lsb = p(BankIdLSB)
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outerParams = p.alterPartial({ case TLId => "L2toMC" })
lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
}
@ -50,7 +50,7 @@ abstract class BaseCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends L
abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
val master = new Bundle {
val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
val mem = Vec(c.nMemChannels, new ClientUncachedTileLinkIO()(outerParams))
val mmio = new ClientUncachedTileLinkIO()(outerMMIOParams)
}
val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
@ -112,14 +112,12 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
// Create a converter between TileLinkIO and MemIO for each channel
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outermostParams))
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerParams))
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
val backendBuffering = TileLinkDepths(0,0,0,0,0)
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
val enqueued = TileLinkEnqueuer(bank.outerTL, backendBuffering)
val unwrapped = TileLinkIOUnwrapper(enqueued)
TileLinkWidthAdapter(icPort, unwrapped)
icPort <> TileLinkIOUnwrapper(enqueued)
}
io.master.mem <> mem_ic.io.out

9
src/main/scala/coreplex/Configs.scala
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@ -132,15 +132,11 @@ class BaseCoreplexConfig extends Config (
nManagers = 1,
nCachingClients = site(NBanksPerMemoryChannel),
nCachelessClients = 0,
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
maxManagerXacts = 1,
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
TileLinkParameters(
coherencePolicy = new MICoherence(
@ -154,7 +150,6 @@ class BaseCoreplexConfig extends Config (
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes) * 8)
}
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case BootROMFile => "./bootrom/bootrom.img"
case NTiles => 1