diff --git a/Makefrag b/Makefrag
index 458da8ef..6f3c3ae1 100644
--- a/Makefrag
+++ b/Makefrag
@@ -537,7 +537,6 @@ al_vvadd.riscv\
 am_matmul.riscv\
 am_vvadd.riscv\
 an_matmul.riscv\
-an_vvadd.riscv\
 ap_matmul.riscv\
 ap_vvadd.riscv\
 aq_matmul.riscv\
diff --git a/emulator/Makefile b/emulator/Makefile
index 269e8e8d..b8589d3d 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -74,7 +74,7 @@ output:
 	mkdir -p $@
 
 output/%.run: output/%.hex emulator
-	./emulator +dramsim +max-cycles=30000000 +coremap-random +loadmem=$< none 2> /dev/null
+	./emulator +dramsim +max-cycles=30000000 +loadmem=$< none 2> /dev/null
 
 output/%.out: output/%.hex emulator
 	./emulator +dramsim +max-cycles=30000000 +verbose +coremap-random +loadmem=$< none 2> $@
diff --git a/riscv-tests b/riscv-tests
index 60f05688..c31d7c5e 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 60f056880ec6929c5f23af4d66aea0f0cb7b0245
+Subproject commit c31d7c5eb4109fdcce58d27b132e20596ece2d07
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 33e12bf4..91137d9e 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -416,7 +416,7 @@ class TopIO(htif_width: Int) extends Bundle  {
 }
 
 object DummyTopLevelConstants extends _root_.uncore.constants.CoherenceConfigConstants {
-  val NTILES = 1
+  val NTILES = 2
   val NBANKS = 1
   val HTIF_WIDTH = 16
   val ENABLE_SHARING = true