riscv/rocket-chip
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Bump chisel3 and firrtl, update plugin versions

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And update chisel3 code
This commit is contained in:
Jack Koenig
2017-08-23 13:33:22 -07:00
committed by Jack Koenig
parent 547bdc2b5b
commit 8891bf1b64
6 changed files with 8 additions and 8 deletions
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src/main/scala/jtag/JtagShifter.scala
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@ -150,7 +150,7 @@ class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V) ex
io.chainOut.data := regs(0)
val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
io.update.bits := io.update.bits.fromBits(updateBits)
io.update.bits := updateBits.asTypeOf(io.update.bits)
val captureBits = io.capture.bits.asUInt()