riscv/rocket-chip
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Reduce node count a bit

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This commit is contained in:
Andrew Waterman 2014-05-25 23:58:25 -07:00
parent 0c93567dea
commit 88899eafe0
1 changed files with 3 additions and 3 deletions
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6
rocket/src/main/scala/btb.scala
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@ -91,8 +91,8 @@ class BTB(implicit conf: BTBConfig) extends Module {
val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0)) val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0)) val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
val useRAS = Mem(Bool(), conf.entries) val useRAS = Reg(UInt(width = conf.entries))
val isJump = Mem(Bool(), conf.entries) val isJump = Reg(UInt(width = conf.entries))
private def page(addr: UInt) = addr >> conf.matchBits private def page(addr: UInt) = addr >> conf.matchBits
private def pageMatch(addr: UInt) = { private def pageMatch(addr: UInt) = {
@ -180,7 +180,7 @@ class BTB(implicit conf: BTBConfig) extends Module {
pageValid := 0 pageValid := 0
} }
io.resp.valid := hits.toBits.orR io.resp.valid := hits.orR
io.resp.bits.taken := io.resp.valid io.resp.bits.taken := io.resp.valid
io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts)) io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
io.resp.bits.entry := OHToUInt(hits) io.resp.bits.entry := OHToUInt(hits)