riscv/rocket-chip
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update README

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Yunsup Lee 2014-08-31 20:57:16 -07:00
parent c03c09ec31
commit 882fecf43a
1 changed files with 3 additions and 10 deletions
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README.md
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@ -15,13 +15,6 @@ To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GN
$ cd riscv-tools $ cd riscv-tools
$ ./build.sh $ ./build.sh
To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):
$ cd riscv-tests/isa/
$ make -j
$ cd riscv-tests/benchmarks
$ make -j
Building The Project Building The Project
-------------------- --------------------
@ -33,7 +26,7 @@ To build the C simulator:
To build the VCS simulator: To build the VCS simulator:
$ cd vlsi/build/vcs-sim-rtl $ cd vsim
$ make $ make
in either case, you can run a set of assembly tests or simple benchmarks: in either case, you can run a set of assembly tests or simple benchmarks:
@ -58,9 +51,9 @@ And to run the assembly tests on the C simulator and generate waveforms:
$ make run-vecasm-timer-tests-debug $ make run-vecasm-timer-tests-debug
$ make run-bmarks-test-debug $ make run-bmarks-test-debug
To get FPGA-synthesizable verilog (output will be in `fpga/generated-src`): To get FPGA-synthesizable verilog (output will be in `fsim/generated-src`):
$ cd fpga/build/syn $ cd fsim
$ make $ make