riscv/rocket-chip
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Scan AddressDecoder bits left to right

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This heuristic is brittle but fixes deduplication in RocketTile.
This commit is contained in:
Andrew Waterman 2017-09-19 17:46:18 -07:00
parent 72bd89a2af
commit 87b92cb206
1 changed files with 3 additions and 3 deletions
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src/main/scala/diplomacy/AddressDecoder.scala
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@ -31,11 +31,11 @@ object AddressDecoder
} } } }
} }
val maxBits = log2Ceil(nonEmptyPorts.map(_.map(_.base).max).max) val maxBits = log2Ceil(1 + nonEmptyPorts.map(_.map(_.base).max).max)
val (bitsToTry, bitsToTake) = (0 to maxBits).map(BigInt(1) << _).partition(b => (givenBits & b) == 0) val (bitsToTry, bitsToTake) = (0 until maxBits).map(BigInt(1) << _).partition(b => (givenBits & b) == 0)
val partitions = Seq(nonEmptyPorts.map(_.sorted).sorted(portOrder)) val partitions = Seq(nonEmptyPorts.map(_.sorted).sorted(portOrder))
val givenPartitions = bitsToTake.foldLeft(partitions) { (p, b) => partitionPartitions(p, b) } val givenPartitions = bitsToTake.foldLeft(partitions) { (p, b) => partitionPartitions(p, b) }
val selected = recurse(givenPartitions, bitsToTry.toSeq) val selected = recurse(givenPartitions, bitsToTry.reverse.toSeq)
val output = selected.reduceLeft(_ | _) | givenBits val output = selected.reduceLeft(_ | _) | givenBits
// Modify the AddressSets to allow the new wider match functions // Modify the AddressSets to allow the new wider match functions