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diplomacy: add NodeHandles to support abstraction

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This commit is contained in:
Wesley W. Terpstra 2016-10-07 23:35:20 -07:00
parent 97af07eb3e
commit 876609eb0e
3 changed files with 28 additions and 7 deletions
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27
src/main/scala/diplomacy/Nodes.scala
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@ -50,8 +50,21 @@ abstract class BaseNode
protected[diplomacy] def colour: String protected[diplomacy] def colour: String
} }
trait InwardNode[DI, UI, BI <: Data] extends BaseNode case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
(inward: InwardNode[DI, UI, BI], outward: OutwardNode[DO, UO, BO])
extends Object with InwardNodeHandle[DI, UI, BI] with OutwardNodeHandle[DO, UO, BO]
trait InwardNodeHandle[DI, UI, BI <: Data]
{ {
val inward: InwardNode[DI, UI, BI]
def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] =
inward.:=(h)(sourceInfo)
}
trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, UI, BI]
{
val inward = this
protected[diplomacy] val numPI: Range.Inclusive protected[diplomacy] val numPI: Range.Inclusive
require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}") require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}") require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
@ -75,8 +88,15 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode
protected[diplomacy] def iConnect: Vec[BI] protected[diplomacy] def iConnect: Vec[BI]
} }
trait OutwardNode[DO, UO, BO <: Data] extends BaseNode trait OutwardNodeHandle[DO, UO, BO <: Data]
{ {
val outward: OutwardNode[DO, UO, BO]
}
trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO, UO, BO]
{
val outward = this
protected[diplomacy] val numPO: Range.Inclusive protected[diplomacy] val numPO: Range.Inclusive
require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}") require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}") require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
@ -136,8 +156,9 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
def iConnect = bundleIn def iConnect = bundleIn
// connects the outward part of a node with the inward part of this node // connects the outward part of a node with the inward part of this node
def := (y: OutwardNode[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = { override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
val x = this // x := y val x = this // x := y
val y = h.outward
val info = sourceLine(sourceInfo, " at ", "") val info = sourceLine(sourceInfo, " at ", "")
require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info) require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
val i = x.iPushed val i = x.iPushed

2
src/main/scala/uncore/axi4/package.scala
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@ -5,5 +5,5 @@ import diplomacy._
package object axi4 package object axi4
{ {
type AXI4OutwardNode = OutwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle] type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
} }

6
src/main/scala/uncore/tilelink2/package.scala
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@ -5,9 +5,9 @@ import diplomacy._
package object tilelink2 package object tilelink2
{ {
type TLOutwardNode = OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle] type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
type TLAsyncOutwardNode = OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle] type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
type IntOutwardNode = OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x) def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None