More WIP on PMP
This commit is contained in:
Andrew Waterman
@ -17,29 +17,80 @@ class PMPConfig extends Bundle {
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val r = Bool()
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}
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object PMP {
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def lgAlign = 2
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}
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class PMP(implicit p: Parameters) extends CoreBundle()(p) {
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import PMP._
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val cfg = new PMPConfig
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val addr = UInt(width = paddrBits - lgAlign)
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def enabled(prv: UInt) = cfg.p.orR && (cfg.m || prv <= PRV.S)
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def locked = cfg.p.andR
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def locked = cfg.p(1)
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def addrLocked(next: PMP) = locked || next.locked && next.cfg.a(1)
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private def lgAlign = 2
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private def mask = (0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt
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private lazy val mask = Cat((0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt, UInt((BigInt(1) << lgAlign) - 1, lgAlign))
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private lazy val comparand = addr << lgAlign
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def pow2AddressMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
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val m = mask
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def checkOne(a: UInt) = (((a >> lgAlign) ^ addr) & ~m) === 0
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var res = checkOne(x)
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for (i <- (1 << lgAlign) until (1 << lgMaxSize) by (1 << lgAlign))
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res = res || (lgSize > log2Ceil(i) && checkOne(x | i))
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res
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private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
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def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0
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if (lgMaxSize <= lgAlign) {
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eval(x, comparand, mask)
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} else {
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// break up the circuit; the MSB part will be CSE'd
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val lsbMask = mask | ~(((BigInt(1) << lgMaxSize) - 1).U << lgSize)
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val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
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val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
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msbMatch && lsbMatch
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}
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}
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def hit(prv: UInt, x: UInt, lgSize: UInt, lgMaxSize: Int) = {
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enabled(prv) && pow2AddressMatch(x, lgSize, lgMaxSize)
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private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
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if (lgMaxSize <= lgAlign) {
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x < comparand
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} else {
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// break up the circuit; the MSB part will be CSE'd
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val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
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val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0
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val lsbsLess = x(lgMaxSize-1, 0) < (comparand(lgMaxSize-1, 0) & lsbMask(lgMaxSize-1, 0))
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msbsLess || (msbsEqual && lsbsLess)
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}
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}
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private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
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!boundMatch(x, ((BigInt(1) << lgMaxSize) - 1).U << lgSize, lgMaxSize)
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private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
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boundMatch(x, ((BigInt(1) << lgMaxSize) - 1).U, lgMaxSize)
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private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
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prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
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private def pow2Homogeneous(x: UInt, pgMask: UInt) = {
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(mask & ~pgMask & (pgMask >> 1.U)) =/= 0 || ((x ^ comparand) & pgMask) =/= 0
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}
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private def rangeHomogeneous(x: UInt, pgMask: UInt, lgMaxSize: Int, prev: PMP) = {
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val beginsAfterLower = !prev.boundMatch(x, ((BigInt(1) << lgMaxSize) - 1).U, lgMaxSize) // CSE with rangeMatch
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val beginsAfterUpper = !boundMatch(x, ((BigInt(1) << lgMaxSize) - 1).U, lgMaxSize) // CSE with rangeMatch
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val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
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val endsBeforeUpper = (x & pgMask) > (comparand & pgMask)
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endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
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}
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def homogeneous(x: UInt, pgMask: UInt, lgMaxSize: Int, prev: PMP): Bool =
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!cfg.p(0) || Mux(cfg.a(1), rangeHomogeneous(x, pgMask, lgMaxSize, prev), pow2Homogeneous(x, pgMask))
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def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = {
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val alignMask = ~(((BigInt(1) << lgMaxSize) - 1).U << lgSize)(lgMaxSize-1, 0)
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val rangeAligned = (prev.comparand(lgMaxSize-1, 0) & alignMask) === 0 && (comparand(lgMaxSize-1, 0) & alignMask) === 0
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val pow2Aligned = (alignMask & ~mask(lgMaxSize-1, 0)) === 0
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Mux(cfg.a(1), rangeAligned, pow2Aligned)
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}
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def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
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cfg.p(0) && Mux(cfg.a(1), rangeMatch(x, lgSize, lgMaxSize, prev), pow2Match(x, lgSize, lgMaxSize))
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}
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class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
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@ -52,15 +103,39 @@ class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
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val r = Bool(OUTPUT)
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val w = Bool(OUTPUT)
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val x = Bool(OUTPUT)
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val pgLevel = UInt(INPUT, log2Ceil(pgLevels))
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val homogeneous = Bool(OUTPUT)
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}
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def hits = io.pmp.map(_.hit(io.prv, io.addr, io.size, lgMaxSize))
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val default = io.prv > PRV.S
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val (r, w, x, _) = ((default, default, default, 0.U) /: (io.pmp zip hits).reverse) { case ((r, w, x, pri), (pmp, hit)) =>
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MuxT(hit && pmp.cfg.p >= pri, (pmp.cfg.r, pmp.cfg.w, pmp.cfg.x, pmp.cfg.p), (r, w, x, pri))
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val pmp0 = Wire(init = 0.U.asTypeOf(new PMP))
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pmp0.cfg.r := default
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pmp0.cfg.w := default
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pmp0.cfg.x := default
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val pgMask = (0 until pgLevels).map { i =>
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val idxBits = pgIdxBits + (pgLevels - 1 - i) * pgLevelBits
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require(idxBits < paddrBits)
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val mask = (BigInt(1) << paddrBits) - (BigInt(1) << idxBits)
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Mux(io.pgLevel >= i, mask.U, 0.U)
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}.reduce(_|_)
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io.homogeneous := ((true.B, pmp0) /: io.pmp) { case ((h, prev), pmp) =>
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(h && pmp.homogeneous(io.addr, pgMask, lgMaxSize, prev), pmp)
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}._1
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val res = (pmp0 /: (io.pmp zip (pmp0 +: io.pmp)).reverse) { case (prev, (pmp, prevPMP)) =>
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val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
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val ignore = default && !pmp.cfg.m
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val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
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val cur = Wire(init = pmp)
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cur.cfg.r := (aligned && pmp.cfg.r) || ignore
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cur.cfg.w := (aligned && pmp.cfg.w) || ignore
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cur.cfg.x := (aligned && pmp.cfg.x) || ignore
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Mux(hit, cur, prev)
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}
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io.r := r
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io.w := w
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io.x := x
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io.r := res.cfg.r
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io.w := res.cfg.w
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io.x := res.cfg.x
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}
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