From d0e350976a367bab2513c5b5b938f2ae5dfac965 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 23 Feb 2018 15:32:10 -0500 Subject: [PATCH 1/2] Add jtag_vpi.c to sources for vsim Signed-off-by: Schuyler Eldridge --- vsim/Makefrag | 1 + 1 file changed, 1 insertion(+) diff --git a/vsim/Makefrag b/vsim/Makefrag index db0e6d4c..8806f561 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -25,6 +25,7 @@ sim_csrcs = \ $(base_dir)/csrc/SimDTM.cc \ $(base_dir)/csrc/SimJTAG.cc \ $(base_dir)/csrc/remote_bitbang.cc \ + $(base_dir)/csrc/jtag_vpi.c #-------------------------------------------------------------------- # Build Verilog From 4bcc42550e9bcc1ccb02085d03961c7dfcd55c19 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 26 Feb 2018 15:12:18 -0500 Subject: [PATCH 2/2] Remove JTAG vpi from VCS build h/t @mwachs5 Signed-off-by: Schuyler Eldridge --- vsim/Makefrag | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/vsim/Makefrag b/vsim/Makefrag index 8806f561..ed58b36c 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -5,7 +5,6 @@ # Verilog sources bb_vsrcs = \ - $(base_dir)/vsrc/jtag_vpi.v \ $(base_dir)/vsrc/plusarg_reader.v \ $(base_dir)/vsrc/ClockDivider2.v \ $(base_dir)/vsrc/ClockDivider3.v \ @@ -24,8 +23,7 @@ sim_vsrcs = \ sim_csrcs = \ $(base_dir)/csrc/SimDTM.cc \ $(base_dir)/csrc/SimJTAG.cc \ - $(base_dir)/csrc/remote_bitbang.cc \ - $(base_dir)/csrc/jtag_vpi.c + $(base_dir)/csrc/remote_bitbang.cc #-------------------------------------------------------------------- # Build Verilog @@ -60,7 +58,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 +libext+.v \ VCS_OPTS += +vpi -VCS_OPTS += -P $(base_dir)/vsrc/jtag_vpi.tab VCS_OPTS += -CC "-DVCS_VPI"