Rename PRCI to CoreplexLocalInterrupter

That's all it's doing (there wasn't much PRC).

src/main/scala/coreplex/Coreplex.scala

@@ -56,7 +56,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
     val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
     val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
     val debug = new DebugBusIO()(p).flip
-    val prci = Vec(c.nTiles, new PRCITileIO).flip
+    val clint = Vec(c.nTiles, new CoreplexLocalInterrupts).asInput
     val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
   }
 
@@ -147,8 +147,8 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
 
     // connect coreplex-internal interrupts to tiles
     for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
-      tileReset := io.prci(i).reset
+      tileReset := reset // TODO should tiles be reset separately from coreplex?
-      tile.io.interrupts := io.prci(i).interrupts
+      tile.io.interrupts := io.clint(i)
       tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
       tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
       tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)

src/main/scala/rocketchip/Periphery.scala

@@ -279,34 +279,34 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
 
 /////
 
-/** Always-ON block */
+trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryParameters {
-trait PeripheryAON extends LazyModule with HasPeripheryParameters {
   implicit val p: Parameters
   val peripheryBus: TLXbar
 
-  // PRCI must be at least XLen in size for atomicity
+  // CoreplexLocalInterrupter must be at least 64b if XLen >= 64
-  val beatBytes = max(innerMMIOParams(XLen)/8, 4)
+  val beatBytes = (innerMMIOParams(XLen) min 64) / 8
-  val prci = LazyModule(new PRCI(PRCIConfig(beatBytes))(innerMMIOParams))
+  val clintConfig = CoreplexLocalInterrupterConfig(beatBytes)
-  // The periphery bus is 32-bit, so we may need to adapt PRCI's width
+  val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(innerMMIOParams))
-  prci.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
+  // The periphery bus is 32-bit, so we may need to adapt its width to XLen
+  clint.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
 
   // TL1 legacy
   val pDevices: ResourceManager[AddrMapEntry]
-  pDevices.add(AddrMapEntry("prci", MemRange(prci.base, prci.size, MemAttr(AddrMapProt.RW))))
+  pDevices.add(AddrMapEntry("clint", MemRange(clintConfig.address, clintConfig.size, MemAttr(AddrMapProt.RW))))
 }
 
-trait PeripheryAONBundle {
+trait PeripheryCoreplexLocalInterrupterBundle {
   implicit val p: Parameters
 }
 
-trait PeripheryAONModule extends HasPeripheryParameters {
+trait PeripheryCoreplexLocalInterrupterModule extends HasPeripheryParameters {
   implicit val p: Parameters
-  val outer: PeripheryAON
+  val outer: PeripheryCoreplexLocalInterrupter
-  val io: PeripheryAONBundle
+  val io: PeripheryCoreplexLocalInterrupterBundle
   val coreplex: Coreplex
 
-  outer.prci.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
+  outer.clint.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
-  coreplex.io.prci <> outer.prci.module.io.tiles
+  coreplex.io.clint <> outer.clint.module.io.tiles
 }
 
 /////

src/main/scala/rocketchip/Top.scala

@@ -84,17 +84,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
 
 /** Example Top with Periphery */
 class ExampleTop(q: Parameters) extends BaseTop(q)
-    with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
+    with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
     with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
   override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
 }
 
 class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
-    with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
+    with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
     with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
 
 class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
-    with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
+    with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
     with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
 
 /** Example Top with TestRAM */

src/main/scala/rocketchip/Utils.scala

@@ -83,7 +83,7 @@ object GenerateConfigString {
   def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
     val addrMap = p(GlobalAddrMap)
     val plicAddr = addrMap("io:int:plic").start
-    val prciAddr = addrMap("io:ext:TL2:prci").start
+    val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
     val xLen = p(XLen)
     val res = new StringBuilder
     res append  "plic {\n"
@@ -92,7 +92,7 @@ object GenerateConfigString {
     res append s"  ndevs ${c.plicKey.nDevices};\n"
     res append  "};\n"
     res append  "rtc {\n"
-    res append s"  addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
+    res append s"  addr 0x${clint.timeAddress.toString(16)};\n"
     res append  "};\n"
     if (addrMap contains "mem") {
       res append  "ram {\n"
@@ -115,8 +115,8 @@ object GenerateConfigString {
       res append s"  $i {\n"
       res append  "    0 {\n"
       res append s"      isa $isa;\n"
-      res append s"      timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
+      res append s"      timecmp 0x${clint.timecmpAddress(i).toString(16)};\n"
-      res append s"      ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
+      res append s"      ipi 0x${clint.msipAddress(i).toString(16)};\n"
       res append s"      plic {\n"
       res append s"        m {\n"
       res append s"         ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"

src/main/scala/uncore/devices/Prci.scala

@@ -14,40 +14,36 @@ import cde.{Parameters, Field}
 /** Number of tiles */
 case object NTiles extends Field[Int]
 
-class PRCITileIO(implicit p: Parameters) extends Bundle {
+class CoreplexLocalInterrupts extends Bundle {
-  val reset = Bool(OUTPUT)
-  val interrupts = new Bundle {
   val mtip = Bool()
   val msip = Bool()
 }
 
-  override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
+case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x44000000) {
-}
+  def msipOffset(hart: Int) = hart * msipBytes
-
+  def msipAddress(hart: Int) = address + msipOffset(hart)
-object PRCI {
+  def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
-  def msip(hart: Int) = hart * msipBytes
+  def timecmpAddress(hart: Int) = address + timecmpOffset(hart)
-  def timecmp(hart: Int) = 0x4000 + hart * timecmpBytes
+  def timeOffset = 0xbff8
-  def time = 0xbff8
+  def timeAddress = address + timeOffset
   def msipBytes = 4
   def timecmpBytes = 8
-  def size = 0xc000
+  def size = 0x10000
 }
 
-case class PRCIConfig(beatBytes: Int, address: BigInt = 0x44000000)
+trait MixCoreplexLocalInterrupterParameters {
-
+  val params: (CoreplexLocalInterrupterConfig, Parameters)
-trait MixPRCIParameters {
-  val params: (PRCIConfig, Parameters)
   val c = params._1
   implicit val p = params._2
 }
 
-trait PRCIBundle extends Bundle with MixPRCIParameters {
+trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters {
-  val tiles = Vec(p(NTiles), new PRCITileIO)
+  val tiles = Vec(p(NTiles), new CoreplexLocalInterrupts).asOutput
   val rtcTick = Bool(INPUT)
 }
 
-trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
+trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCoreplexLocalInterrupterParameters {
-  val io: PRCIBundle
+  val io: CoreplexLocalInterrupterBundle
 
   val timeWidth = 64
   val time = Reg(init=UInt(0, width = timeWidth))
@@ -57,15 +53,14 @@ trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
   val ipi     = Seq.fill(p(NTiles)) { RegInit(UInt(0, width = 1)) }
 
   for ((tile, i) <- io.tiles zipWithIndex) {
-    tile.interrupts.msip := ipi(i)(0)
+    tile.msip := ipi(i)(0)
-    tile.interrupts.mtip := time >= timecmp(i)
+    tile.mtip := time >= timecmp(i)
-    tile.reset := reset
   }
 
   def pad = RegField(8) // each use is a new field
   val ipi_fields = ipi.map(r => Seq(RegField(1, r), RegField(7), pad, pad, pad)).flatten
   val timecmp_fields = timecmp.map(RegField.bytes(_)).flatten
-  val time_fields = Seq.fill(PRCI.time%c.beatBytes)(pad) ++ RegField.bytes(time)
+  val time_fields = Seq.fill(c.timeOffset % c.beatBytes)(pad) ++ RegField.bytes(time)
 
   /* 0000 msip hart 0
    * 0004 msip hart 1
@@ -77,8 +72,8 @@ trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
    * bffc mtime hi
    */
   val ipi_base     = 0
-  val timecmp_base = PRCI.timecmp(0) / c.beatBytes
+  val timecmp_base = c.timecmpOffset(0) / c.beatBytes
-  val time_base    = PRCI.time       / c.beatBytes
+  val time_base    = c.timeOffset / c.beatBytes
 
   regmap((
     RegField.split(ipi_fields,     ipi_base,     c.beatBytes) ++
@@ -88,7 +83,7 @@ trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
 
 /** Power, Reset, Clock, Interrupt */
 // Magic TL2 Incantation to create a TL2 Slave
-class PRCI(c: PRCIConfig)(implicit val p: Parameters)
+class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p: Parameters)
-  extends TLRegisterRouter(c.address, 0, 0x10000, None, c.beatBytes, false)(
+  extends TLRegisterRouter(c.address, 0, c.size, None, c.beatBytes, false)(
-  new TLRegBundle((c, p), _)    with PRCIBundle)(
+  new TLRegBundle((c, p), _)    with CoreplexLocalInterrupterBundle)(
-  new TLRegModule((c, p), _, _) with PRCIModule)
+  new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)