riscv/rocket-chip
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Rename PRCI to CoreplexLocalInterrupter

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That's all it's doing (there wasn't much PRC).
This commit is contained in:
Andrew Waterman
2016-09-16 14:26:34 -07:00
parent 4b1de82c1d
commit 86b70c8c59
5 changed files with 50 additions and 55 deletions
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57
src/main/scala/uncore/devices/Prci.scala
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@ -14,40 +14,36 @@ import cde.{Parameters, Field}
/** Number of tiles */
case object NTiles extends Field[Int]
class PRCITileIO(implicit p: Parameters) extends Bundle {
val reset = Bool(OUTPUT)
val interrupts = new Bundle {
val mtip = Bool()
val msip = Bool()
}
override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
class CoreplexLocalInterrupts extends Bundle {
val mtip = Bool()
val msip = Bool()
}
object PRCI {
def msip(hart: Int) = hart * msipBytes
def timecmp(hart: Int) = 0x4000 + hart * timecmpBytes
def time = 0xbff8
case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x44000000) {
def msipOffset(hart: Int) = hart * msipBytes
def msipAddress(hart: Int) = address + msipOffset(hart)
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
def timecmpAddress(hart: Int) = address + timecmpOffset(hart)
def timeOffset = 0xbff8
def timeAddress = address + timeOffset
def msipBytes = 4
def timecmpBytes = 8
def size = 0xc000
def size = 0x10000
}
case class PRCIConfig(beatBytes: Int, address: BigInt = 0x44000000)
trait MixPRCIParameters {
val params: (PRCIConfig, Parameters)
trait MixCoreplexLocalInterrupterParameters {
val params: (CoreplexLocalInterrupterConfig, Parameters)
val c = params._1
implicit val p = params._2
}
trait PRCIBundle extends Bundle with MixPRCIParameters {
val tiles = Vec(p(NTiles), new PRCITileIO)
trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters {
val tiles = Vec(p(NTiles), new CoreplexLocalInterrupts).asOutput
val rtcTick = Bool(INPUT)
}
trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
val io: PRCIBundle
trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCoreplexLocalInterrupterParameters {
val io: CoreplexLocalInterrupterBundle
val timeWidth = 64
val time = Reg(init=UInt(0, width = timeWidth))
@ -57,15 +53,14 @@ trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
val ipi = Seq.fill(p(NTiles)) { RegInit(UInt(0, width = 1)) }
for ((tile, i) <- io.tiles zipWithIndex) {
tile.interrupts.msip := ipi(i)(0)
tile.interrupts.mtip := time >= timecmp(i)
tile.reset := reset
tile.msip := ipi(i)(0)
tile.mtip := time >= timecmp(i)
}
def pad = RegField(8) // each use is a new field
val ipi_fields = ipi.map(r => Seq(RegField(1, r), RegField(7), pad, pad, pad)).flatten
val timecmp_fields = timecmp.map(RegField.bytes(_)).flatten
val time_fields = Seq.fill(PRCI.time%c.beatBytes)(pad) ++ RegField.bytes(time)
val time_fields = Seq.fill(c.timeOffset % c.beatBytes)(pad) ++ RegField.bytes(time)
/* 0000 msip hart 0
* 0004 msip hart 1
@ -77,8 +72,8 @@ trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
* bffc mtime hi
*/
val ipi_base = 0
val timecmp_base = PRCI.timecmp(0) / c.beatBytes
val time_base = PRCI.time / c.beatBytes
val timecmp_base = c.timecmpOffset(0) / c.beatBytes
val time_base = c.timeOffset / c.beatBytes
regmap((
RegField.split(ipi_fields, ipi_base, c.beatBytes) ++
@ -88,7 +83,7 @@ trait PRCIModule extends Module with HasRegMap with MixPRCIParameters {
/** Power, Reset, Clock, Interrupt */
// Magic TL2 Incantation to create a TL2 Slave
class PRCI(c: PRCIConfig)(implicit val p: Parameters)
extends TLRegisterRouter(c.address, 0, 0x10000, None, c.beatBytes, false)(
new TLRegBundle((c, p), _) with PRCIBundle)(
new TLRegModule((c, p), _, _) with PRCIModule)
class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p: Parameters)
extends TLRegisterRouter(c.address, 0, c.size, None, c.beatBytes, false)(
new TLRegBundle((c, p), _) with CoreplexLocalInterrupterBundle)(
new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)