riscv/rocket-chip
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Rename PRCI to CoreplexLocalInterrupter

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That's all it's doing (there wasn't much PRC).
This commit is contained in:
Andrew Waterman
2016-09-16 14:26:34 -07:00
parent 4b1de82c1d
commit 86b70c8c59
5 changed files with 50 additions and 55 deletions
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28
src/main/scala/rocketchip/Periphery.scala
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@ -279,34 +279,34 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
/////
/** Always-ON block */
trait PeripheryAON extends LazyModule with HasPeripheryParameters {
trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryParameters {
implicit val p: Parameters
val peripheryBus: TLXbar
// PRCI must be at least XLen in size for atomicity
val beatBytes = max(innerMMIOParams(XLen)/8, 4)
val prci = LazyModule(new PRCI(PRCIConfig(beatBytes))(innerMMIOParams))
// The periphery bus is 32-bit, so we may need to adapt PRCI's width
prci.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
// CoreplexLocalInterrupter must be at least 64b if XLen >= 64
val beatBytes = (innerMMIOParams(XLen) min 64) / 8
val clintConfig = CoreplexLocalInterrupterConfig(beatBytes)
val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(innerMMIOParams))
// The periphery bus is 32-bit, so we may need to adapt its width to XLen
clint.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
// TL1 legacy
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("prci", MemRange(prci.base, prci.size, MemAttr(AddrMapProt.RW))))
pDevices.add(AddrMapEntry("clint", MemRange(clintConfig.address, clintConfig.size, MemAttr(AddrMapProt.RW))))
}
trait PeripheryAONBundle {
trait PeripheryCoreplexLocalInterrupterBundle {
implicit val p: Parameters
}
trait PeripheryAONModule extends HasPeripheryParameters {
trait PeripheryCoreplexLocalInterrupterModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryAON
val io: PeripheryAONBundle
val outer: PeripheryCoreplexLocalInterrupter
val io: PeripheryCoreplexLocalInterrupterBundle
val coreplex: Coreplex
outer.prci.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
coreplex.io.prci <> outer.prci.module.io.tiles
outer.clint.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
coreplex.io.clint <> outer.clint.module.io.tiles
}
/////

6
src/main/scala/rocketchip/Top.scala
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@ -84,17 +84,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
/** Example Top with Periphery */
class ExampleTop(q: Parameters) extends BaseTop(q)
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
}
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
/** Example Top with TestRAM */

8
src/main/scala/rocketchip/Utils.scala
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@ -83,7 +83,7 @@ object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:int:plic").start
val prciAddr = addrMap("io:ext:TL2:prci").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"
@ -92,7 +92,7 @@ object GenerateConfigString {
res append s" ndevs ${c.plicKey.nDevices};\n"
res append "};\n"
res append "rtc {\n"
res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
res append s" addr 0x${clint.timeAddress.toString(16)};\n"
res append "};\n"
if (addrMap contains "mem") {
res append "ram {\n"
@ -115,8 +115,8 @@ object GenerateConfigString {
res append s" $i {\n"
res append " 0 {\n"
res append s" isa $isa;\n"
res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
res append s" timecmp 0x${clint.timecmpAddress(i).toString(16)};\n"
res append s" ipi 0x${clint.msipAddress(i).toString(16)};\n"
res append s" plic {\n"
res append s" m {\n"
res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"